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? 2015 microchip technology inc. ds00001621b-page 1 general description the CAP1166, which incorporates righttouch ? tech- nology, is a multiple channel capacitive touch sensor with multiple power led drivers. it contains six (6) indi- vidual capacitive touch sensor inputs with programma- ble sensitivity for use in touch sensor applications. each sensor input automati cally recalibrates to com- pensate for gradual environmental changes. the CAP1166 also contains six (6) led drivers that offer full-on / off, variable rate blinking, dimness con- trols, and breathing. each of the led drivers may be linked to one of the sensor inputs to be actuated when a touch is detected. as we ll, each led driver may be individually controlled via a host controller. the CAP1166 includes multiple pattern touch recogni- tion that allows the user to select a specific set of but- tons to be touched simultaneously. if this pattern is detected, then a status bit is set and an interrupt gen- erated. additionally, the CAP1166 includes circuitry and sup- port for enhanced sensor proximity detection. the CAP1166 offers multiple power states operating at low quiescent currents. in the standby state of opera- tion, one or more capacitive touch sensor inputs are active and all leds may be used. if a touch is detected, it will wake the system us ing the wake/spi_mosi pin. deep sleep is the lowest po wer state available, draw- ing 5ua (typical) of current. in this state, no sensor inputs are active. drivi ng the wake/spi_mosi pin or communications will wake the device. applications ? desktop and notebook pcs ? lcd monitors ? consumer electronics ? appliances features ? six (6) capacitive touch sensor inputs - programmable sensitivity - automatic recalibration - individual thresholds for each button ? proximity detection ? multiple button pattern detection ? calibrates for parasitic capacitance ? analog filtering for system noise sources ? press and hold feature for volume-like applica- tions ? multiple communication interfaces - smbus / i 2 c compliant interface - spi communications - pin selectable communications protocol and multiple slave addresses (smbus / i 2 c only) ? low power operation - 5ua quiescent current in deep sleep - 50ua quiescent current in standby (1 sensor input monitored) - samples one or more channels in standby ? six (6) led driver outputs - open drain or push-pull - programmable blink, breathe, and dimness controls - can be linked to capacitive touch sensor inputs ? dedicated wake output flags touches in low power state ? system reset pin ? available in 20-pin 4mm x 4mm qfn or 24-pin ssop rohs compliant package CAP1166 6 channel capacitive touch sensor with 6 led drivers
CAP1166 ds00001621b-page 2 ? 2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2015 microchip technology inc. ds00001621b-page 3 CAP1166 table of contents 1.0 block diagram ............................................................................................................. .................................................................... 4 2.0 pin description ........................................................................................................... ..................................................................... 5 3.0 electrical specif ications ................................................................................................. ................................................................. 9 4.0 communications ............................................................................................................ ............................................................... 12 5.0 general description ....................................................................................................... ............................................................... 23 6.0 register description ...................................................................................................... ................................................................ 29 7.0 package information ....................................................................................................... .............................................................. 67 appendix a: device delta ...................................................................................................... ............................................................. 72 appendix b: data sheet revision history ....................................................................................... .................................................... 74 the microchip web site ........................................................................................................ .............................................................. 76 customer change notification service .......................................................................................... ..................................................... 76 customer support .............................................................................................................. ................................................................. 76 product identification system ................................................................................................. ............................................................ 77
? 2015 microchip technology inc. ds00001621b-page 4 CAP1166 1.0 block diagram smbus / bc-link or spi slave protocol smclk / bc_clk / spi_clk smdata bc_data / spi_msio/ spi_miso vdd gnd alert# / bc_irq# capacitive touch sensing algorithm led1 cs1 cs2 cs3 cs4 cs5 cs6 led driver, breathe, and dimness control wake / spi_mosi reset addr_comm spi_cs# led2 led3 led4 led5 led6
CAP1166 ds00001621b-page 5 ? 2015 microchip technology inc. 2.0 pin description figure 2-1: CAP1166 pin diagram (20-pin qfn) 1 2 3 4 15 14 13 12 20 19 18 17 6 7 8 9 5 10 11 16 CAP1166 20 pin qfn gnd led4 led3 led2 led6 led5 smclk / bc_clk / spi_clk wake / spi_mosi spi_cs# led1 smdata / bc_data / spi_msio / spi_miso cs1 cs2 cs3 reset cs6 cs5 addr_comm cs4 alert# / bc_irq# vdd
? 2015 microchip technology inc. ds00001621b-page 6 CAP1166 figure 2-2: CAP1166 pin diagram (24-pin ssop) table 2-1: pin description for CAP1166 pin number (qfn 20) pin number (ssop 24) pin name pin function pin type unused connection 1 4 spi_cs# active low chip-s elect for spi bus di (5v) connect to ground 25 wake / spi_- mosi wake - active high wake / interrupt output standby power state - requires pull-down resistor wake - active high wake input - require s pull-down resistor deep sleep power state do pull-down resistor di spi_mosi - spi master-out-s lave-in port when used in normal mode di (5v) connect to gnd CAP1166 24 ssop 24 23 22 21 20 17 19 18 16 13 15 14 1 2 3 4 5 8 6 7 9 12 10 11 cs1 reset spi_cs# wake / spi_mosi smdata /spi_msio / spi_miso smclk / spi_clk led1 led2 led3 gnd led4 gnd led5 led6 alert# / bc_irq# addr_comm cs6 cs5 cs4 cs3 cs2 vdd n/c n/c
CAP1166 ds00001621b-page 7 ? 2015 microchip technology inc. 36 smdata / spi_msio / spi_miso smdata - bi-directional, open-drain smbus data - requires pull-up resistor diod (5v) n/a spi_msio - spi master-slave -in-out bidirectional port when used in bi-directional mode dio spi_miso - spi master-in-slave-out port when used in normal mode do 48 smclk / spi_clk smclk - smbus clock input - requires pull-up resistor di (5v) n/a spi_clk - spi clock input di (5v) 59led1 open drain led 1 driver (default) od (5v) connect to ground push-pull led 1 driver do leave open or connect to ground 610led2 open drain led 2 driver (default) od (5v) connect to ground push-pull led 2 driver do leave open or connect to ground 711led3 open drain led 3 driver (default) od (5v) connect to ground push-pull led 3 driver do leave open or connect to ground 813led4 open drain led 4 driver (default) od (5v) connect to ground push-pull led 4 driver do leave open or connect to ground 915led5 open drain led 5 driver (default) od (5v) connect to ground push-pull led 5 driver do leave open or connect to ground 10 16 led6 open drain led 6 driver (default) od (5v) connect to ground push-pull led 6 driver do leave open or connect to ground table 2-1: pin description for CAP1166 (continued) pin number (qfn 20) pin number (ssop 24) pin name pin function pin type unused connection
? 2015 microchip technology inc. ds00001621b-page 8 CAP1166 application note: when the alert# pinis configured as an active low output, it will be open drain. when it is configured as an active high output, it will be push-pull. application note: for the 5v tolerant pins that have a pull-up re sistor, the pull-up voltage must not exceed 3.6v when the CAP1166 is unpowered. application note: the spi_cs# pin should be grounded when smbus, or i 2 c,communications are used. the pin types are described in table 2-2 . all pins labeled with (5v) are 5v tolerant. 11 17 alert# alert# - active low alert / interrupt output for smbus alert or spi interrupt - requires pull-up resistor (default) od (5v) connect to gnd alert# - active high push-pull alert / interrupt output for smbus alert or spi interrupt do high-z 12 18 addr_ comm address / communications select pin - pull-down resis- tor determines address / communications mechanism ai n/a 13 19 cs6 capacitive touch sensor input 6 aio connect to ground 14 20 cs5 capacitive touch sensor input 5 aio connect to ground 15 21 cs4 capacitive touch sensor input 4 aio connect to ground 16 22 cs3 capacitive touch sensor input 3 aio connect to ground 17 23 cs2 capacitive touch sensor input 2 aio connect to ground 18 24 cs1 capacitive touch sensor input 1 aio connect to ground 19 1 vdd positive power supply power n/a 20 1 reset active high soft reset for syst em - resets all registers to default values. if not used, connect to ground. di (5v) connect to ground bottom pad 12 gnd ground power n/a 14 gnd ground power n/a table 2-1: pin description for CAP1166 (continued) pin number (qfn 20) pin number (ssop 24) pin name pin function pin type unused connection
CAP1166 ds00001621b-page 9 ? 2015 microchip technology inc. table 2-2: pin types pin type description power this pin is used to supply power or ground to the device. di digital input - this pin is used as a digital input. this pin is 5v tolerant. aio analog input / output -this pin is used as an i/o for analog signals. diod digital input / open drain output - this pin is used as a digital i/o. wh en it is used as an out- put, it is open drain and requires a pull- up resistor. this pin is 5v tolerant. od open drain digital output - this pin is used as a digital output. it is open drain and requires a pull-up resistor. this pin is 5v tolerant. do push-pull digital output - this pin is used as a digital output and can sink and source current. dio push-pull digital input / output - this pin is used as an i/o for digital signals.
? 2015 microchip technology inc. ds00001621b-page 10 CAP1166 3.0 electrical specifications note 3-1 stresses above those listed could cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. note 3-2 for the 5v tolerant pins that have a pull- up resistor, the voltage difference between v 5vt_pin and v dd must never exceed 3.6v. note 3-3 the package power dissipation specification assumes a recommended thermal via design consisting of a 3x3 matrix of 0.3m m (12mil) vias at 1.0mm pitch connected to the ground plane with a 2.5 x 2.5mm thermal landing. note 3-4 junction to ambient ( ja ) is dependent on the design of the thermal vias. without thermal vias and a thermal landing, the ja is approximately 60c/w including localized pcb temp erature increase. table 3-1: absolute maximum ratings voltage on 5v tolerant pins (v 5vt_pin ) -0.3 to 5.5 v voltage on 5v tolerant pins (|v 5vt_pin - v dd |) note 3-2 0 to 3.6 v voltage on vdd pin -0.3 to 4 v voltage on any other pin to gnd -0.3 to vdd + 0.3 v package power dissipation up to t a = 85c for 20 pin qfn (see note 3-3 ) 0.9 w junction to ambient ( ja ) (see note 3-4 )58 c/w operating ambient temperature range -40 to 125 c storage temperature range -55 to 150 c esd rating, all pins, hbm 8000 v
CAP1166 ds00001621b-page 11 ? 2015 microchip technology inc. table 3-2: electrical specifications v dd = 3v to 3.6v, t a = 0c to 85c, all typical values at t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions dc power supply voltage v dd 3.0 3.3 3.6 v supply current i stby 120 170 ua standby state active 1 sensor input monitored no leds active default conditions (8 avg, 70ms cycle time) i stby 50 ua standby state active 1 sensor input monitored no leds active 1 avg, 140ms cycle time, i dsleep 515ua deep sleep state active leds at 100% or 0% duty cycle no communications t a < 40c 3.135 < v dd < 3.465v i dd 500 600 ua capacitive sensing active no leds active capacitive touch sensor inputs maximum base capacitance c base 50 pf pad untouched minimum detectable capacitive shift c touch 20 ff pad touched - default conditions (1 avg, 35ms cycle time, 1x sensitiv- ity) recommended cap shift c touch 0.1 2 pf pad touched - not tested power supply rejec- tion psr 3 10 counts / v untouched current counts base capacitance 5pf - 50pf maximum sensitivity negative delta counts disabled all other parameters default timing reset pin delay t rst_dly 10 ms time to communica- tions ready t comm_dly 15 ms time to first conver- sion ready t conv_dly 170 200 ms led drivers duty cycle duty led 0 100 % programmable drive frequency f led 2khz sinking current i sink 24 ma v ol = 0.4 sourcing current i source 24 ma v oh = v dd - 0.4 leakage current i leak 5 ua powered or unpowered ta < 85c pull-up voltage < 3.6v if unpowered i/o pins output low voltage v ol 0.4 v i sink_io = 8ma output high voltage v oh v dd - 0.4 v i source_io = 8ma
? 2015 microchip technology inc. ds00001621b-page 12 CAP1166 note 3-5 the alert pin will not glitch high or low at powe r up if connected to vdd or another voltage. note 3-6 the smclk and smdata pins will not g litch low at power up if connec ted to vdd or another voltage. input high voltage v ih 2.0 v input low voltage v il 0.8 v leakage current i leak 5 ua powered or unpowered t a < 85c pull-up voltage < 3.6v if unpowered reset pin release to conversion ready t reset 170 200 ms smbus timing input capacitance c in 5pf clock frequency f smb 10 400 khz spike suppression t sp 50 ns bus free time stop to start t buf 1.3 us start setup time t su:sta 0.6 us start hold time t hd:sta 0.6 us stop setup time t su:sto 0.6 us data hold time t hd:dat 0 us when transmitting to the master data hold time t hd:dat 0.3 us when receiving from the master data setup time t su:dat 0.6 us clock low period t low 1.3 us clock high period t high 0.6 us clock / data fall time t fall 300 ns min = 20+0.1c load ns clock / data rise time t rise 300 ns min = 20+0.1c load ns capacitive load c load 400 pf per bus line spi timing clock period t p 250 ns clock low period t low 0.4 x t p 0.6 x t p ns clock high period t high 0.4 x t p 0.6 x t p ns clock rise / fall time t rise / t fall 0.1 x t p ns data output delay t d:clk 10 ns data setup time t su:dat 20 ns data hold time t hd:dat 20 ns spi_cs# to spi_clk setup time t su:cs 0ns wake time t wake 10 20 us spi_cs# asserted to clk assert table 3-2: electrical specifications (continued) v dd = 3v to 3.6v, t a = 0c to 85c, all typical values at t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions
? 2015 microchip technology inc. ds00001621b-page 13 CAP1166 4.0 communications 4.1 communications the CAP1166communicates using the 2-wire smbus or i 2 c bus, the 2-wire proprietary bc-link, or the spi bus. if the proprietary bc-link protocol is requir ed for your application, please contact yo ur microchip representative for ordering instructions. regardless of communication mechanism, th e device functionality remains unchanged. the communica- tions mechanism as well as the smbus (or i 2 c) slave address is determined by the resistor connected between the addr_comm pin and ground as shown in table 4-1 . 4.1.1 smbus (i 2 c) communications when configured to communicate via the smbus, the cap1 166 supports the following protocols: send byte, receive byte, read byte, write byte, read block, and write block. in addition, the device supports i 2 c formatting for block read and block write protocols. application note: for smbus/i 2 c communications, the spi_cs# pin is not used and should be grounded; any data presented to this pin will be ignored. see section 4.2 and section 4.3 for more information on the smbus bus and protocols respectively. 4.1.2 spi communications when configured to communicate via the spi bus, the cap1 166supports both bi-directional 3-wire and normal 4-wire protocols and uses the spi_cs# pin to enable communications. application note: see section 4.5 and section 4.6 for more information on the spi bus and protocols respectively.upon power up, the CAP1166 will not respond to any communications for up to 15ms. after this time, full functionality is available. 4.2 system management bus the CAP1166 communicates with a host controller, such as an sio, through the smbus. the smbus is a two-wire serial communication protocol between a computer host and its pe ripheral devices. a detailed timing diagram is shown in figure 4-1 . stretching of the smclk signal is supported; howev er, the CAP1166 will not stretch the clock signal. table 4-1: addr_comm pin decode pull-down resistor (+/- 5%) protocol used smbus address gnd spi communications using normal 4-wire protocol used n/a 56k spi communications using bi- directional 3-wire protocol used n/a 68k reserved n/a 82k smbus / i 2 c 0101_100(r/w) 100k smbus / i 2 c 0101_011(r/w) 120k smbus / i 2 c 0101_010(r/w) 150k smbus / i 2 c 0101_001(r/w) vdd smbus / i 2 c 0101_000(r/w)
CAP1166 ds00001621b-page 14 ? 2015 microchip technology inc. 4.2.1 smbus start bit the smbus start bit is defined as a transition of the smbus da ta line from a logic ?1? state to a logic ?0? state while the smbus clock line is in a logic ?1? state. 4.2.2 smbus address and rd / wr bit the smbus address byte consists of the 7-bit slave address followed by the rd / wr indicator bit. if this rd / wr bit is a logic ?0?, then the smbus host is writin g data to the slave device. if this rd / wr bit is a logic ?1?, then the smbus host is reading data from the slave device. see table 4-1 for available smbus addresses. 4.2.3 smbus data bytes all smbus data bytes are sent most significant bi t first and composed of 8-bits of information. 4.2.4 smbus ack and nack bits the smbus slave will acknowledge all data bytes that it re ceives. this is done by the slave device pulling the smbus data line low after the 8th bit of each by te that is transmitted. this applies to both the write byte and block write proto- cols. the host will nack (not acknowledge) the last data byte to be received from the slave by holding the smbus data line high after the 8th data bit has been sent. for the block read pr otocol, the host will ack each data byte that it receives except the last data byte. 4.2.5 smbus stop bit the smbus stop bit is defined as a transition of the smbus da ta line from a logic ?0? state to a logic ?1? state while the smbus clock line is in a logic ?1? state. when the CAP1166 detects an smbus stop bit and it has been communicating with the smbus protocol, it will reset its slave interf ace and prepare to receive further communications. 4.2.6 smbus timeout the CAP1166 includes an smbus timeout feature. followin g a 30ms period of inactivity on the smbus where the smclk pin is held low, the device will timeout and reset the smbus interface. the timeout function defaults to disabled . it can be enabled by setting the ti meout bit in the configuration register (see section 6.6, "config uration registers" ). 4.2.7 smbus and i 2 c compatibility the major differences between smbus and i 2 c devices are highlighted here. for more information, refer to the smbus 2.0 and i 2 c specifications. for information on using the CAP1166 in an i 2 c system, refer to an 14.0 dedicated slave devices in i 2 c systems. figure 4-1: smbus timing diagram smdata smclk t low t rise t high t fall t buf t hd:sta p s s - start condition p - stop condition t hd:dat t su:dat t su:sta t hd:sta p t su:sto s
? 2015 microchip technology inc. ds00001621b-page 15 CAP1166 1. CAP1166 supports i 2 c fast mode at 400khz. this covers the smbus max time of 100khz. 2. minimum frequency for smbu s communications is 10khz. 3. the smbus slave protocol will reset if the clock is held at a logic ?0? for longer than 30ms. this timeout function- ality is disabled by default in the CAP1166 and can be enabled by writing to the timeout bit. i 2 c does not have a timeout. 4. the smbus slave protocol will reset if both the clock an d data lines are held at a logic ?1? for longer than 200s (idle condition). this function is disabled by default in the CAP1166 and can be enabled by writing to the time- out bit. i 2 c does not have an idle condition. 5. i 2 c devices do not support the alert response address functionality (which is optional for smbus). 6. i 2 c devices support block read and write differently. i 2 c protocol allows for unlimited number of bytes to be sent in either direction. the smbus protocol requires that an additional data byte indicating number of bytes to read / write is transmitted. the CAP1166 supports i 2 c formatting only. 4.3 smbus protocols the CAP1166 is smbus 2.0 compatible and supports write byte, read byte, send byte, and receive byte as valid protocols as shown below. all of the below protocols use the convention in table 4-2 . 4.3.1 smbus write byte the write byte is used to write one byte of data to a specific register as shown in ta b l e 4 - 3 . 4.3.2 smbus read byte the read byte protocol is used to read one byte of data from the registers as shown in table 4-4 . 4.3.3 smbus send byte the send byte protocol is used to set the internal address register pointer to the correct address location. no data is transferred during the send byte protocol as shown in ta b l e 4 - 5 . application note: the send byte protocol is not functional in deep sleep (i.e., dsleep bit is set). table 4-2: protocol format data sent to device data sent to the host data sent data sent table 4-3: write byte protocol start slave address wr ack register address ack register data ack stop 1 ->0 yyyy_yyy 0 0 xxh 0 xxh 0 0 -> 1 table 4-4: read byte protocol start slave address wr ack register address ack start slave address rd ack register data nack stop 1->0 yyyy_yyy 0 0 xxh 0 1 ->0 yyyy_yyy 1 0 xxh 1 0 -> 1 table 4-5: send byte protocol start slave address wr ack register address ack stop 1 -> 0 yyyy_yyy 0 0 xxh 0 0 -> 1
CAP1166 ds00001621b-page 16 ? 2015 microchip technology inc. 4.3.4 smbus receive byte the receive byte protocol is used to read data from a register when the intern al register address pointer is known to be at the right location (e.g., set via send byte). this is us ed for consecutive reads of the same register as shown in table 4-6 . application note: the receive byte protocol is not functional in deep sleep (i.e., dsleep bit is set). 4.4 i 2 c protocols the CAP1166 supports i 2 c block write and block read. the protocols listed below use the convention in ta b l e 4 - 2 . 4.4.1 block write the block write is used to write multiple data byte s to a group of contiguous registers as shown in ta b l e 4 - 7 . application note: when using the block write protocol, the in ternal address pointer will be automatically incremented after every data byte is received. it will wrap from ffh to 00h. 4.4.2 block read the block read is used to read multiple data bytes from a group of contiguous registers as shown in table 4-8 . application note: when using the block read protocol, the internal address pointer will be automatically incremented after every data byte is received. it will wrap from ffh to 00h. 4.5 spi interface the smbus has a predefined packet struct ure, the spi does not. the spi bus can operate in two modes of operation, normal 4-wire mode and bi-directional 3-wire mode. all spi co mmands consist of 8-bit packets sent to a specific slave device (identified by the cs pin). the spi bus will latch data on the rising edge of the clock and the clock and data both idle high. all commands are supported via both oper ating modes. the support ed commands are: reset serial interface, set address pointer, write command and read command. note that all other codes received during the command phase are ignored and have no effect on the operation of the device. table 4-6: receive byte protocol start slave address rd ack register data nack stop 1 -> 0 yyyy_yyy 1 0 xxh 1 0 -> 1 table 4-7: block write protocol start slave address wr ack register address ack register data ack 1 ->0 yyyy_yyy 0 0 xxh 0 xxh 0 register data ack register data ack . . . register data ack stop xxh 0 xxh 0 . . . xxh 0 0 -> 1 table 4-8: block read protocol start slave address wr ack register address ack start slave address rd ack register data 1->0 yyyy_yyy 0 0 xxh 0 1 ->0 yyyy_yyy 1 0 xxh ack register data ack register data ack register data ack . . . register data nack stop 0 xxh 0 xxh 0 xxh 0 . . . xxh 1 0 -> 1
? 2015 microchip technology inc. ds00001621b-page 17 CAP1166 4.5.1 spi normal mode the spi bus can operate in two modes of operation, normal and bi-directional mode. in the normal mode of operation, there are dedicated input and output data lines. th e host communicates by sendi ng a command along the CAP1166 spi_mosi data line and reading data on the spi_miso data li ne. both communications occur simultaneously which allows for larger throughput of data transactions. all basic transfers consist of two 8 bit transactions from the master device while the slave device is simultaneously send- ing data at the current address pointer value. data writes consist of two or more 8-bit transactions. the host sends a specific write command followed by the data to write the address pointer. data reads consist of one or more 8-bit transactions. the host sends the specific read data command and continues clocking for as many data bytes as it wishes to receive. 4.5.2 spi bi-directional mode in the bi-directional mode of operation, the spi data signal s are combined into the spi_msio line, which is shared for data received by the device and transmitted by the device . the protocol uses a simple handshake and turn around sequence for data communications based on the number of clocks transmitted during each phase. all basic transfers consist of two 8 bit transactions. the first is an 8 bit command phase driven by the master device. the second is by an 8 bit data phase driven by the master for writes, and by the CAP1166 for read operations. the auto increment feature of the address pointer allows for successive reads or writes. the address pointer will return to 00h after reaching ffh. 4.5.3 spi_cs# pin the spi bus is a single master, multiple slave serial bus. ea ch slave has a dedicated cs pi n (chip select) that the master asserts low to identify that the slave is being add ressed. there are no formal addressing options. 4.5.4 address pointer all data writes and reads are accessed from the current addr ess pointer. in both bi-directional mode and full duplex mode, the address pointer is automatically incremente d following every read command or every write command. the address pointer will return to 00h after reaching ffh. 4.5.5 spi timeout the CAP1166 does not detect any ti meout conditions on the spi bus. figure 4-2: spi timing spi_msio or spi_mosi or spi_miso spi_clk t low t rise t high t fall t d:clk t hd:dat t su:dat t p
? 2015 microchip technology inc. ds00001621b-page 18 CAP1166 4.6 normal spi protocols when operating in normal mode, the spi bus internal address pointer is incremented depending upon which command has been transm itted. multiple commands may be transmitted sequentually so long as the spi_cs# pin is asserted low. figure 4-3 shows an example of this operation. 4.6.1 reset interface resets the serial interface whenever two successive 7ah codes ar e received. regardless of the cu rrent phase of the transaction - command or data, the receipt of the successive reset commands resets the serial communication interface only. all ot her functions are not affected by the reset ope ration. figure 4-3: example spi bus communication - normal mode spi_cs# spi_miso spi_mosi spi address pointer spi data output buffer register address / data 7ah xxh (invalid) xxh (invalid) yyh (invalid) 7ah 7dh 41h yyh (invalid) 7eh 66h xxh (invalid) 45h 7dh 41h aah (invalid) aah (invalid) 7fh 7fh 55h (invalid) 66h 7fh aah 7dh 43h 40h 78h 7fh xxh (invalid) 7fh 56h 40h / 56h 41h / 45h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 45h 40h / 56h 41h / 45h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h / 78h 42h aah 40h / 56h 41h / 66h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 55h 7fh aah 40h / 56h 41h / 66h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 66h 42h aah 40h / 56h 41h / 66h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h / 78h 40h / 56h 41h / 66h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h / 78h 40h / 56h 41h / 66h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h /78h 44h 80h 40h 80h 40h 56h 40h / 56h 41h / 66h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h /78h 43h 55h 7fh 7fh 55h 40h / 56h 41h / 66h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h /78h 80h 45h 43h 46h 78h 40h / 56h 41h / 66h 42h / aah 43h / 55h 44h / 80h 45h / 43h 46h / 78h 00h xxh indicates spi address pointer incremented
? 2015 microchip technology inc. ds00001621b-page 19 CAP1166 4.6.2 set address pointer the set address pointer command sets the address pointer fo r subsequent reads and writes of data. the pointer is set on the rising edge of the final data bit. at the same time, the data that is to be read is fetched and loaded into the internal output buffer but is not transmitted. 4.6.3 write data the write data protocol updates the contents of the register referenced by the address pointer. as the command is pro- cessed, the data to be read is fetched and loaded into the in ternal output buffer but not tr ansmitted. then, the register is updated with the data to be written. finally, the address pointer is incremented. figure 4-4: spi reset interface co mmand - normal mode figure 4-5: spi set address pointer command - normal mode master spdout spi_mosi spi_cs# spi_clk reset - 7ah reset - 7ah invalid register data 00h ? internal data buffer empty spi_miso master drives slave drives ?0? ?1? ?1? ?1? ?1? ?0? ?1? ?0? ?0? ?1? ?1? ?1? ?1? ?0? ?1? ?0? master spdout spi_mosi register address spi_cs# spi_clk set address pointer ? 7dh unknown, invalid data unknown, invalid data spi_miso master drives slave drives address pointer set ?0? ?0? ?1? ?1? ?1? ?1? ?1? ?1?
CAP1166 ds00001621b-page 20 ? 2015 microchip technology inc. 4.6.4 read data the read data protocol is used to read data from the de vice. during the normal mode of operation, while the device is receiving data, the CAP1166 is simultaneously transmitting da ta to the host. for the set address commands and the write data commands, this data may be invalid and it is recommended that the read data command is used. figure 4-6: spi write command - normal mode figure 4-7: spi read command - normal mode master spdout spi_mosi data to write spi_cs# spi_clk write command ? 7eh unknown, invalid data old data at current address pointer spi_miso master drives slave drives 1. data written at current address pointer 2. address pointer incremented master spdout spi_mosi master drives slave drives spi_clk first read command ? 7fh spi_cs# invalid, unknown data * spi_miso ?0? ?1? ?1? ?1? ?1? ?1? ?1? ?1? subsequent read commands ? 7f data at current address pointer address pointer incremented ** ?0? ?1? ?1? ?1? ?1? ?1? ?1? ?1? * the first read command after any other command will return invalid data for the first byte. subsequent read commands w ill return the data at the current address pointer ** the address pointer is incremented 8 clocks after the read command has been received. therefore continually sending read commands w ill result in each comm and reporting new data. once read commands have been finished, the last data byte w ill be read during the next 8 clocks for any command
? 2015 microchip technology inc. ds00001621b-page 21 CAP1166 4.7 bi-directional spi protocols 4.7.1 reset interface resets the serial interface whenever two successive 7ah c odes are received. regardless of the current phase of the transaction - command or data, the receipt of the successive reset commands resets the serial communication interface only. all other functions are not affected by the reset operation. 4.7.2 set address pointer sets the address pointer to the register to be accessed by a read or write command. this command overrides the auto- incrementing of the address pointer. figure 4-8: spi read command - normal mode - full figure 4-9: spi reset interface command - bi-directional mode mast er spdout spi_mosi master drives slave drives spi_clk read command ? 7fh spi_cs# data at previously set register address = current address pointer spi_miso ?0? ?1? ?1? ?1? ?1? ?1? ?1? ?1? data at previously set register address = current address pointer (spi) xxh 1. register read address updated to current spi read address pointer 1. register data loaded into output buffer = data at current address pointer 1. output buffer transmitted = data at previous address pointer + 1 = current address pointer 1. register read address incremented = current address pointer + 1 1. spi read address incremented = new current address pointer 2. register read address incremented = current address pointer +1 register data loaded into output buffer = data at current address pointer + 1 1. output buffer transmitted = data at current address pointer + 1 2. flag set to increment spi read address at end of next 8 clocks ?0? ?1? ?1? ?1? ?1? ?1? ?1? ?1? data at previously set register address = current address pointer (spi) 1. register data loaded into output buffer = data at current address pointer 1. output buffer transmitted = data at previous register address pointer + 1 = current address pointer 1. output buffer transmitted = data at current address pointer + 1 2. flag set to increment spi read address at end of next 8 clocks subsequent read commands ? 7fh 1. register read address updated to current spi read address pointer. 2. register read address incremented = current address pointer +1 ? end result = register address pointer doesn?t change master spdout spi_msio spi_cs# spi_clk reset - 7ah reset - 7ah ?1? ?1? ?1? ?1? ?1? ?0? ?0? ?0? ?1? ?1? ?1? ?1? ?1? ?0? ?0? ?0?
CAP1166 ds00001621b-page 22 ? 2015 microchip technology inc. 4.7.3 write data writes data value to the register address stored in the addre ss pointer. performs auto increment of address pointer after the data is loaded into the register. 4.7.4 read data reads data referenced by the address pointer. performs auto increment of address pointer after the data is transferred to the master. figure 4-10: spi set address pointer co mmand - bi-directional mode figure 4-11: spi write data command - bi-directional mode figure 4-12: spi read data command - bi-directional mode master spdout spi_msio register address spi_cs# spi_clk set address pointer ? 7dh ?0? ?1? ?0? ?1? ?1? ?1? ?1? ?1? master spdout spi_msio register write data spi_cs# spi_clk write command ? 7eh ?1? ?1? ?1? ?1? ?1? ?1? ?0? ?0? mast er spdout spi_msio master drives slave drives indeterminate register read data spi_clk read command ? 7fh spi_cs# ?0? ?1? ?1? ?1? ?1? ?1? ?1? ?1?
? 2015 microchip technology inc. ds00001621b-page 23 CAP1166 4.8 bc-link interface the bc-link is a proprietary bus developed to allow comm unication between a host controller device to a companion device. this device uses this serial bus to read and writ e registers and for interrupt proc essing. the interface uses a data port concept, where the base interface has an address regi ster, data register and a control register, defined in the 8051?s sfr space. refer to documentation for the bc-link compatible host controller for details on how to access the CAP1166 via the bc- link interface.
? 2015 microchip technology inc. ds00001621b-page 24 CAP1166 5.0 general description the CAP1166 is a multiple channel capacitive touch sensor with multiple power led drivers. it contains six (6) individ- ual capacitive touch sensor inputs with programmable sensit ivity for use in touch sensor applications. each sensor input automatically recalibrates to compensa te for gradual environmental changes. the CAP1166 also contains six (6) low side (or push-pull) led dr ivers that offer full-on / off, variable rate blinking, dim- ness controls, and breathing. each of the led drivers may be lin ked to one of the sensor inputs to be actuated when a touch is detected. as well, each led driver ma y be individually controlled via a host controller. finally, the device contains a dedicated reset pin to act as a soft reset by the system. the CAP1166 offers multiple power states. it operates at t he lowest quiescent current during its deep sleep state. in the low power standby state, it can monitor one or more channels and respond to communications normally. the device contains a wake pin (wake/spi_mosi) ou tput to wake the system when a touch is detected in standby and to wake the device from deep sleep. the device communicates with a host contro ller using the spi bus, or via smbus / i 2 c. the host controller may poll the device for updated information at any time or it may config ure the device to flag an interrupt whenever a touch is detected on any sensor pad. a typical system diagram is shown in figure 5-1 .
CAP1166 ds00001621b-page 25 ? 2015 microchip technology inc. 5.1 power states the CAP1166 has three operating states depending on the status of the stby and dsleep bits. when the device tran- sitions between power states, previously det ected touches (for inactive channels) are cleared and the status bits reset. 1. fully active - the device is fully active. it is monitoring all active capacitive sensor inputs and driving all led chan- nels as defined. 2. standby - the device is in a lower power state. it will measure a programmable nu mber of channels using the standby configuration controls (see section 6.20 through section 6.22 ). interrupts will still be generated based on the active channels. the device will still respond to co mmunications normally and can be returned to the fully figure 5-1: system diagram for CAP1166 CAP1166 cs4 smdata / bc_data / spi_msio / spi_miso smclk / bc_clk / spi_clk embedded controller vdd alert# / bc_irq# cs5 cs6 3.3v ? 5v cs3 cs2 cs1 wake / spi_mosi reset spi_cs# addr_comm led6 led5 led4 led1 led2 led3 3.3v ? 5v touch button touch button touch button touch button touch button touch button
? 2015 microchip technology inc. ds00001621b-page 26 CAP1166 active state of operation by clearing the stby bit. 3. deep sleep - the device is in its lowest power state. it is not monitoring any capacitive sensor inputs and not driving any leds. all leds will be driven to their prog rammed non-actuated state and no pwm operations will be done. while in deep sleep, the device can be awakened by smbus or spi communications targeting the device. this will not cause the dsleep to be cleared so the device will return to deep sleep once all communi- cations have stopped. if the device is not communicati ng via the 4-wire spi bus, then during this state of operation, if the wake/spi_mosi pin is driven high by an external source, the device will cl ear the dsleep bit and return to fully active. application note: in the deep sleep state, the le d output will be either high or low and will not be pwm?d at the min or max duty cycle. 5.2 reset pin the reset pin is an active high reset that is driven from an external source. whil e it is asserted hi gh, all the internal blocks will be held in reset including the communications protocol used. no capacitive touch sensor inputs will be sam- pled and the leds will not be driven. al l configuration settings will be reset to default states and all readings will be cleared. the device will be held in deep sleep that can only be re moved by driving the reset pin low. this will cause the reset status bit to be set to a logic ?1? and generate an interrupt. 5.3 wake/spi_mosi pin operation the wake / spi_mosi pin is a multi-function pin depending on de vice operation. when the device is configured to com- municate using the 4-wire spi bus, this pin is an input. however, when the CAP1166 is placed in standby and is not communicating using the 4-wire spi protocol, the wake pin is an active high output. in this condition, the device will assert the wake/spi_mosi pin when a touch is detected on one of its sampled sensor inputs. the pin will remain a sserted until the int bit has been cleared and then it will be de-asserted. when the CAP1166 is placed in deep sleep and it is not co mmunicating using the 4-wire spi protocol, the wake/spi_- mosi pin is monitored by the device as an input. if the wa ke/spi_mosi pin is driven high by an external source, the CAP1166will clear th e dsleep bit causing the device to return to fully active. when the device is placed in deep sleep, this pin is a high-z input and must have a pull-down resistor to gnd for proper operation. 5.4 led drivers the CAP1166 contains six (6) led drivers. each led driver ca n be linked to its respective capacitive touch sensor input or it can be controlled by the host. ea ch led driver can be configured to ope rate in one of the following modes with either push-pull or open drain drive. 1. direct - the led is configured to be on or off when the co rresponding input stimulus is on or off (or inverted). the brightness of the led can be programmed from full off to full on (default). additionally , the led contains controls to individually configure ramping on, off, and turn-off delay. 2. pulse 1 - the led is configured to ?pulse? (transit ion on-off-on) a programmabl e number of times with pro- grammable rate and min / max brightness. this behavior may be actuated when a press is detected or when a release is detected. 3. pulse 2 - the led is configured to ?pulse? while actuat ed and then ?pulse? a programmable number of times with programmable rate and min / max brightness when the sensor pad is released. 4. breathe - the led is configured to transition continuously on-off-on (i.e . to ?breathe?) with a programmable rate and min / max brightness. when an led is not linked to a sensor and is actuated by the host, there?s an option to assert the alert# pin when the initiated led behavior has completed. 5.4.1 linking leds to capacitive touch sensor inputs all leds can be linked to the corresponding capacitive touch s ensor input so that when the sensor input detects a touch, the corresponding led will be actuated at one of the programmed responses.
CAP1166 ds00001621b-page 27 ? 2015 microchip technology inc. 5.5 capacitive touch sensing the CAP1166 contains six (6) independent capacitive touch sensor inputs. each sensor input has dynamic range to detect a change of capacitance due to a touch. additionally , each sensor input can be configured to be automatically and routinely re-calibrated. 5.5.1 sensing cycle each capacitive touch sensor input has controls to be activated and included in the sensi ng cycle. when the device is active, it automatically initiates a sensing cycle and repeats the cycle every time it finishes. the cycle polls through each active sensor input starting with cs1 and extending through cs 6. as each capacitive touch sensor input is polled, its measurement is compared against a baseline ?not touched? measurement. if the delta measurement is large enough, a touch is detected and an interrupt is generated. the sensing cycle time is programmable (see section 6.10, "averaging and sa mpling configuration register" ). 5.5.2 recalibrating sensor inputs there are various options for recalibrating the capacitive to uch sensor inputs. recalibration re-sets the base count reg- isters ( section 6.24, "sensor input base count registers" ) which contain the ?not touched? values used for touch detec- tion comparisons. application note: the device will recalibrate all sensor inputs that were disabled when it transitions from standby. likewise, the device will recalibrate all sensor inputs when waking out of deep sleep. 5.5.2.1 manual recalibration the calibration activate registers ( section 6.11, "calibration activate register" ) force recalibration of selected sensor inputs. when a bit is set, the corresponding capacitive touch sensor input will be recalibrated (both analog and digital). the bit is automatically cleared once t he recalibration routine has finished. 5.5.2.2 automatic recalibration each sensor input is regularly reca librated at a programmable rate (see section 6.17, "recalibration configuration reg- ister" ). by default, the recalibration routine stores the aver age 64 previous measurements and periodically updates the base ?not touched? setting for the capacitive touch sensor input. 5.5.2.3 negative delta count recalibration it is possible that the device loses sensitivity to a touch. this may happen as a result of a noisy environment, an acci- dental recalibration during a touch, or other environmental ch anges. when this occurs, the base untouched sensor input may generate negative delta count values. the neg_delta_cnt bits (see section 6.17, "recalibration configuration register" ) can be set to force a recalibration after a spec ified number of consecutiv e negative delta readings. 5.5.2.4 delayed recalibration it is possible that a ?stuck button? occu rs when something is placed on a button which causes a touch to be detected for a long period. by setting the max_dur_en bit (see section 6.6, "configuration registers" ), a recalibration can be forced when a touch is held on a button for longer than the duration specified in the max_dur bits (see section 6.8, "sensor input confi guration register" ). note: during this recalibration routine, the sensor inputs will not detect a press for up to 200ms and the sensor base count register values will be invalid. in addition, any press on the corresponding sensor pads will invalidate the recalibration. note: automatic recalibration only works when the delta count is below the active sensor input threshold. it is dis- abled when a touch is detected. note: during this recalibration, the device will not respond to touches.
? 2015 microchip technology inc. ds00001621b-page 28 CAP1166 5.5.3 proximity detection each sensor input can be configured to detect changes in capa citance due to proximity of a touch. this circuitry detects the change of capacitance that is gener ated as an object approaches, but does no t physically touch, the enabled sensor pad(s). when a sensor input is selected to perform proximity detection, it will be sampled from 1x to 128x per sampling cycle. the larger the number of samples th at are taken, the gr eater the range of proximity de tection is available at the cost of an increased overall sampling time. 5.5.4 multiple touch pattern detection the multiple touch pattern (mtp) detection circuitry can be used to detect lid closure or other similar events. an event can be flagged based on either a minimum number of sensor inputs or on specific sensor inputs simultaneously exceed- ing an mtp threshold or having their noise flag status register bits set. an interrupt can also be generated. during an mtp event, all touches are blocked (see section 6.15, "multiple touch pa ttern configuration register" ). 5.5.5 low frequency noise detection each sensor input has an emi noise detector that will sense if low frequency noise is injected onto the input with suffi- cient power to corrupt the readings. if this occurs, the device will reject the corrupted sample and set the corresponding bit in the noise status register to a logic ?1?. 5.5.6 rf noise detection each sensor input contains an integrated rf noise detector . this block will detect injected rf noise on the cs pin. the detector threshold is dependent upon the noise frequency. if rf no ise is detected on a cs line, that sample is removed and not compared against the threshold. 5.6 alert# pin the alert# pin is an active low (or active high when co nfigured) output that is dr iven when an interrupt event is detected. whenever an interrupt is generated, the int bit (see section 6.1, "main control register" ) is set. the alert# pin is cleared when the int bit is cleared by the user. additionally, wh en the int bit is cleared by the user, status bits are only cleared if no touch is detected. 5.6.1 sensor interrupt behavior the sensor interrupts are generated in one of two ways: 1. an interrupt is generated when a touch is detected and, as a user selectable option, when a release is detected (by default - see section 6.6 ). see figure 5-3 . 2. if the repeat rate is enabled then, so long as the touch is held, another interrupt will be generated based on the programmed repeat rate (see figure 5-2 ). when the repeat rate is enabled, the device uses an additional control called mpress that determines whether a touch is flagged as a simple ?touch? or a ?press and hold?. the mpress[3:0] bits set a minimum press timer. when the button is touched, the timer begins. if the sens or pad is released before the minimum press timer expires, it is flagged as a touch and an interrupt is generated upon rele ase. if the sensor input detects a touch for longer than this timer value, it is flagged as a ?press and hold? event. so long as the touc h is held, interrupts will be generated at the programmed repeat rate and upon release (if enabled). application note: figure 5-2 and figure 5-3 show default operation which is to generate an interrupt upon sensor pad release and an active-low alert# pin. application note: the host may need to poll the device twice to determine that a release has been detected. note: delayed recalibration only works when the delta count is above the active sens or input threshold. if enabled, it is invoked when a sensor pad touc h is held longer than the max_dur bit setting.
CAP1166 ds00001621b-page 29 ? 2015 microchip technology inc. figure 5-2: sensor interrupt behavior - repeat rate enabled figure 5-3: sensor interrupt behavior - no repeat rate enabled touch detected int bit button status write to int bit polling cycle (35ms) min press setting (280ms) interrupt on touch button repeat rate (175ms) button repeat rate (175ms) interrupt on release (optional) alert# pin (active low) touch detected int bit button status write to int bit polling cycle (35ms) interrupt on touch interrupt on release (optional) alert# pin (active low)
? 2015 microchip technology inc. ds00001621b-page 30 CAP1166 6.0 register description the registers shown in ta b l e 6 - 1 are accessible through the communications prot ocol. an entry of ?-? indicates that the bit is not used and will always read ?0?. table 6-1: register set in hexadecimal order register address r/w register name functi on default value page 00h r/w main control controls general power states and power dissipation 00h page 33 02h r general status stores general status bits 00h page 34 03h r sensor input status returns the state of the sampled capacitive touch sensor inputs 00h page 34 04h r led status stores status bits for leds 00h page 34 0ah r noise flag status stores the noise flags for sensor inputs 00h page 35 10h r sensor input 1 delta count stores the delta count for cs1 00h page 35 11h r sensor input 2 delta count stores the delta count for cs2 00h page 35 12h r sensor input 3 delta count stores the delta count for cs3 00h page 35 13h r sensor input 4 delta count stores the delta count for cs4 00h page 35 14h r sensor input 5 delta count stores the delta count for cs5 00h page 35 15h r sensor input 6 delta count stores the delta count for cs6 00h page 35 1fh r/w sensitivity control controls the sensitiv ity of the threshold and delta counts and data scaling of the base counts 2fh page 36 20h r/w configuration controls general functionality 20h page 37 21h r/w sensor input enable controls whether the capacitive touch sensor inputs are sampled 3fh page 38 22h r/w sensor input configura- tion controls max duration and auto-repeat delay for sensor inputs operating in the full power state a4h page 39 23h r/w sensor input configura- tion 2 controls the mpress controls for all sensor inputs 07h page 40 24h r/w averaging and sam- pling config controls averaging and sampling win- dow 39h page 41 26h r/w calibration activate forces re-calibrati on for capacitive touch sensor inputs 00h page 42 27h r/w interrupt enable enables interrupts associated with capacitive touch sensor inputs 3fh page 42 28h r/w repeat rate enable enables repeat rate for all sensor inputs 3fh page 43 2ah r/w multiple touch configu- ration determines the number of simultane- ous touches to flag a multiple touch condition 80h page 43 2bh r/w multiple touch pattern configuration determines the multiple touch pattern (mtp) configuration 00h page 44
CAP1166 ds00001621b-page 31 ? 2015 microchip technology inc. 2dh r/w multiple touch pattern determines the pattern or number of sensor inputs used by the mtp cir- cuitry 3fh page 45 2fh r/w recalibration configura- tion determines re-calibration timing and sampling window 8ah page 45 30h r/w sensor input 1 thresh- old stores the delta count threshold to determine a touch for capacitive touch sensor input 1 40h page 47 31h r/w sensor input 2 thresh- old stores the delta count threshold to determine a touch for capacitive touch sensor input 2 40h page 47 32h r/w sensor input 3 thresh- old stores the delta count threshold to determine a touch for capacitive touch sensor input 3 40h page 47 33h r/w sensor input 4 thresh- old stores the delta count threshold to determine a touch for capacitive touch sensor input 4 40h page 47 34h r/w sensor input 5 thresh- old stores the delta count threshold to determine a touch for capacitive touch sensor input 5 40h page 47 35h r/w sensor input 6 thresh- old stores the delta count threshold to determine a touch for capacitive touch sensor input 6 40h page 47 38h r/w sensor input noise threshold stores controls for selecting the noise threshold for all sensor inputs 01h page 47 standby configuration registers 40h r/w standby channel controls which sensor inputs are enabled while in standby 00h page 47 41h r/w standby configuration controls averaging and cycle time while in standby 39h page 48 42h r/w standby sensitivity controls sensitivity settings used while in standby 02h page 49 43h r/w standby threshold stores the touch detection threshold for active sensor inputs in standby 40h page 50 44h r/w configuration 2 stores additional configuration con- trols for the device 40h page 37 base count registers 50h r sensor input 1 base count stores the reference count value for sensor input 1 c8h page 50 51h r sensor input 2 base count stores the reference count value for sensor input 2 c8h page 50 52h r sensor input 3 base count stores the reference count value for sensor input 3 c8h page 50 53h r sensor input 4 base count stores the reference count value for sensor input 4 c8h page 50 54h r sensor input 5 base count stores the reference count value for sensor input 5 c8h page 50 55h r sensor input 6 base count stores the reference count value for sensor input 6 c8h page 50 table 6-1: register set in hexadecimal order (continued) register address r/w register name functi on default value page
? 2015 microchip technology inc. ds00001621b-page 32 CAP1166 led controls 71h r/w led output type controls the output type for the led outputs 00h page 50 72h r/w sensor input led link- ing controls linking of sensor inputs to led channels 00h page 51 73h r/w led polarity controls the output polarity of leds 00h page 51 74h r/w led output control controls the output state of the leds 00h page 52 77h r/w linked led transition control controls the transition when leds are linked to cs channels 00h page 53 79h r/w led mirror control controls the mirroring of duty cycles for the leds 00h page 54 81h r/w led behavior 1 controls the behavior and response of leds 1 - 4 00h page 55 82h r/w led behavior 2 controls the behavior and response of leds 5 - 6 00h page 55 84h r/w led pulse 1 period controls the period of each breathe during a pulse 20h page 56 85h r/w led pulse 2 period controls the period of the breathing during breathe and pulse operation 14h page 58 86h r/w led breathe period controls the period of an led breathe operation 5dh page 59 88h r/w led config controls led configuration 04h page 59 90h r/w led pulse 1 duty cycle determines the min and max duty cycle for the pulse operation f0h page 60 91h r/w led pulse 2 duty cycle determines the min and max duty cycle for breathe and pulse operation f0h page 60 92h r/w led breathe duty cycle determines the min and max duty cycle for the breat he operation f0h page 60 93h r/w led direct duty cycle determines the min and max duty cycle for direct mode led operation f0h page 60 94h r/w led direct ramp rates determines the rising and falling edge ramp rates of the leds 00h page 61 95h r/w led off delay determines the off delay for all led behaviors 00h page 61 b1h r sensor input 1 calibra- tion stores the upper 8-bit calibration value for sensor input 1 00h page 64 b2h r sensor input 2 calibra- tion stores the upper 8-bit calibration value for sensor input 2 00h page 64 b3h r sensor input 3 calibra- tion stores the upper 8-bit calibration value for sensor input 3 00h page 64 b4h r sensor input 4 calibra- tion stores the upper 8-bit calibration value for sensor input 4 00h page 64 b5h r sensor input 5 calibra- tion stores the upper 8-bit calibration value for sensor input 5 00h page 64 b6h r sensor input 6 calibra- tion stores the upper 8-bit calibration value for sensor input 6 00h page 64 b9h r sensor input calibra- tion lsb 1 stores the 2 lsbs of the calibration value for sensor inputs 1 - 4 00h page 64 table 6-1: register set in hexadecimal order (continued) register address r/w register name functi on default value page
CAP1166 ds00001621b-page 33 ? 2015 microchip technology inc. during power-on-reset (por), the default values are stored in the registers. a por is in itiated when power is first applied to the part and the voltage on the vdd supply surpa sses the por level as specified in the electrical character- istics. any reads to undefined registers will return 00h. writes to undefined registers will not have an effect. when a bit is ?set?, this means that the us er writes a logic ?1? to it. when a bit is ?cleared?, this means that the user write s a logic ?0? to it. 6.1 main control register the main control register controls the primary power state of the device. bits 7 - 6 - gain[1:0] - controls the gain used by the capaciti ve touch sensing circuitry. as the gain is increased, the effective sensitivity is likewise increased as a smaller delt a capacitance is required to generate the same delta count values. the sensitivity settings may need to be adjusted alon g with the gain settings such that data overflow does not occur. application note: the gain settings apply to both standby and active states. bit 5 - stby - enables standby. ? ?0? (default) - sensor input scanning is active and leds are functional. ? ?1? - capacitive touch sensor input scanning is limited to the sensor inputs set in the standby channel register (see section 6.20 ). the status registers will not be cleared until read. leds that are linked to capacitive touch sensor inputs will remain linked and active. sensor inputs that are no longer sampled will flag a release and then remain in a non-touched state. leds that ar e manually controlled will be unaffected. ? bit 4 - dsleep - enables deep sleep by deactivating all functions. this bi t will be cleared when the wake pin is driven high. ?0? (default) - sensor input scanning is active and leds are functional. ? ?1? - all sensor input scanning is di sabled. all leds are driven to their programmed non-actuat ed state and no pwm operations will be done. the stat us registers are automat ically cleared and the int bit is cleared. bit 0 - int - indicates that there is an interrupt. when this bi t is set, it asserts the alert# pin. if a channel detects a touch and its associated interrupt enable bit is not set to a logic ?1?, no action is taken. bah r sensor input calibra- tion lsb 2 stores the 2 lsbs of the calibration value for sensor inputs 5 - 6 00h page 64 fdh r product id stores a fixed value that identifies each product 51h page 65 feh r manufacturer id stores a fixed value that identifies microchip 5dh page 65 ffh r revision stores a fixed value that represents the revision number 83h page 65 table 6-2: main control register addrr/w register b7 b6b5 b4 b3b2b1b0default 00h r/w main control gain[1:0] stby dsleep - - - int 00h table 6-3: gain bit decode gain[1:0] capacitive touch sensor gain 10 00 1 01 2 10 4 11 8 table 6-1: register set in hexadecimal order (continued) register address r/w register name functi on default value page
? 2015 microchip technology inc. ds00001621b-page 34 CAP1166 this bit is cleared by writing a logic ?0? to it. when this bit is cleared, the alert# pin will be deasserted and all status registers will be cleared if the condition has been removed. if the wake/spi_mosi pin is asserted as a result of a touch detected while in standby, it will likewis e be deasserted when this bit is cleared. note that the wake / spi_mosi pin is not driven when communicating via th e 4-wire spi protocol. ? ?0? - no interrupt pending. ? ?1? - a touch has been detected on one or more channels and the interrupt has been asserted. 6.2 status registers all status bits are cleared when the devi ce enters the deep sl eep (dsleep = ?1? - see section 6.1 ). 6.2.1 general status - 02h bit 4 - led - indicates that one or more leds have finished th eir programmed activity. this bit is set if any bit in the led status register is set. bit 3 - reset - indicates that the device has come out of reset. this bit is set when the device exits a por state or when the reset pin has been deasserted and qualified via the reset pin filter (see section 5.2 ). this bit will cause the int bit to be set and is cleared when the int bit is cleared. bit 2 - mult - indicates that the device is blocking detect ed touches due to the multiple touch detection circuitry (see section 6.14 ). this bit will not cause the int bit to be set and hence will not cause an interrupt. bit 1 - mtp - indicates that the device has detected a number of sensor inputs th at exceed the mtp threshold either via the pattern recognition or via t he number of sensor inputs (see section 6.15 ). this bit will cause the int bit to be set if the mtp_alert bit is also set. this bit will not be cleared un til the condition that caused it to be set has been removed. bit 0 - touch - indicates that a touch was de tected. this bit is set if any bit in the sensor input status register is set. 6.2.2 sensor input status - 03h the sensor input status register stores status bits that indicate a touch has b een detected. a value of ?0? in any bit indicates that no touch has been detected. a value of ?1? in any bit indicates that a touch has been detected. all bits are cleared when the int bit is cleared and if a touch on the respective capacitive touch sensor input is no longer present. if a touch is st ill detected, the bits will not be cleared (but this will not cause the interrupt to be asserted - see section 6.6 ). bit 5 - cs6 - indicates that a touch was detected on sensor input 6. this sensor input can be linked to led6. bit 4 - cs5 - indicates that a touch was detected on sensor input 5. this sensor input can be linked to led5. bit 3 - cs4 - indicates that a touch was detected on sensor input 4. this sensor input can be linked to led4. bit 2 - cs3 - indicates that a touch was detected on sensor input 3. this sensor input can be linked to led3. bit 1 - cs2 - indicates that a touch was detected on sensor input 2. this sensor input can be linked to led2. bit 0 - cs1 - indicates that a touch was detected on sensor input 1. this sensor input can be linked to led1. 6.2.3 led status - 04h the led status registers indicate when an le d has completed its configured behavior (see section 6.31, "led behav- ior registers" ) after being actuated by the host (see section 6.28, "led output control register" ). these bits are ignored when the led is linked to a capacitive sensor input. a ll led status bits are cleared when the int bit is cleared. bit 5 - led6_dn - indicates that led6 has fini shed its behavior after being actuated by the host. bit 4 - led5_dn - indicates that led5 has fini shed its behavior after being actuated by the host. table 6-4: status registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 02h r general status - - - led reset mult mtp touch 00h 03h r sensor input sta- tus - - cs6 cs5 cs4 cs3 cs2 cs1 00h 04h r led status - - led6_ dn led5_ dn led4_ dn led3_ dn led2_ dn led1_ dn 00h
CAP1166 ds00001621b-page 35 ? 2015 microchip technology inc. bit 3 - led4_dn - indicates that led4 has fini shed its behavior after being actuated by the host. bit 2 - led3_dn - indicates that led3 has fini shed its behavior after being actuated by the host. bit 1 - led2_dn - indicates that led2 has fini shed its behavior after being actuated by the host. bit 0 - led1_dn - indicates that led1 has fini shed its behavior after being actuated by the host. 6.3 noise flag status registers the noise flag status registers store stat us bits that are generated from the analog block if the detected noise is above the operating region of the analog detector or the rf noise detector. these bits indi cate that the most recently received data from the sensor input is invalid and should not be used for touch detection. so long as the bit is set for a particular channel, the delta count value is reset to 00h and thus no touch is detected. these bits are not sticky and will be cl eared automatically if the analog block does not report a noise error. application note: if the mtp detection circuitry is enabled, thes e bits count as sensor inputs above the mtp threshold (see section 5.5.4, "multiple touch pattern detection" ) even if the corresponding delta count is not. if the corresponding delta co unt also exceeds the mtp threshold, it is not counted twice. application note: regardless of the state of t he noise status bits, if low frequency noise is detected on a sensor input, that sample will be discarded unless the dis_ana_noise bit is set. as well, if rf noise is detected on a sensor i nput, that sample will be discarded unless the dis_rf_noise bit is set. 6.4 sensor input delta count registers the sensor input delta count registers store the delta count that is compared against the threshold used to determine if a touch has been detected. the count value represents a change in input due to the capacitance associated with a touch on one of the sensor inputs and is referenced to a calibrated base ?not touched? count value. the delta is an instantaneous change and is updated once per sensor input per sensing cycle (see section 5.5.1, "sensing cycle" ). the value presented is a standard 2?s complement number. in addition, the value is capped at a value of 7fh. a reading of 7fh indicates that the sensitivity settings are too high and should be adjusted accordingly (see section 6.5 ). the value is also capped at a negative value of 80h for negative delta counts which may result upon a release. table 6-5: noise flag status registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 0ah r noise flag status --cs6_ noise cs5_ noise cs4_ noise cs3_ noise cs2_ noise cs1_ noise 00h table 6-6: sensor input delta count registers addrr/w register b7 b6 b5b4b3b2b1b0default 10h r sensor input 1 delta count sign 64 32 16 8 4 2 1 00h 11h r sensor input 2 delta count sign 64 32 16 8 4 2 1 00h 12h r sensor input 3 delta count sign 64 32 16 8 4 2 1 00h 13h r sensor input 4 delta count sign 64 32 16 8 4 2 1 00h 14h r sensor input 5 delta count sign 64 32 16 8 4 2 1 00h 15h r sensor input 6 delta count sign 64 32 16 8 4 2 1 00h
? 2015 microchip technology inc. ds00001621b-page 36 CAP1166 6.5 sensitivity control register the sensitivity control regi ster controls the sensitiv ity of a touch detection. bits 6-4 delta_sense[2:0] - controls th e sensitivity of a touch det ection. the sensitivity settings act to scale the rel- ative delta count value higher or lower based on the system parameters. a setting of 000b is the most sensitive while a setting of 111b is the least sensitive. at the more sensitive settings, touches are detected for a smaller delta capacitance corresponding to a ?lighter? touch. these settings are more sensitive to noise, however, and a noisy environment may flag more false touches with higher sensitivity levels. application note: a value of 128x is the most sens itive setting available. at the most sensitivity settings, the msb of the delta count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a c of 25ff from a 10pf base capacitance). conversely, a value of 1x is t he least sensitive setting available. at these settings, the msb of the delta count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a c of 3.33pf from a 10pf base capacitance). bits 3 - 0 - base_shift[3:0] - controls the scaling and data presenta tion of the base count re gisters. the higher the value of these bits, the larger the range and the lower the resolution of th e data presented. the scale factor represents the multiplier to the bit-weighting pres ented in these register descriptions. application note: the base_shift[3:0] bits normall y do not need to be updated. t hese settings will not affect touch detection or sensitivity. these bits ar e sometimes helpful in analyzing the cap sensing board performance and stability. table 6-7: sensitivit y control register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 1fh r/w sensitivity control - del ta_sense[2:0] base_shift[3:0] 2fh table 6-8: delta_sense bit decode delta_sense[2:0] sensitivity multiplier 210 0 0 0 128x (most sensitive) 001 64x 0 1 0 32x (default) 011 16x 100 8x 101 4x 110 2x 1 1 1 1x - (least sensitive) table 6-9: base_shift bit decode base_shift[3:0] data scaling factor 32 1 0 00 0 0 1x 00 0 1 2x 00 1 0 4x 00 1 1 8x 01 0 0 16x 01 0 1 32x 01 1 0 64x
CAP1166 ds00001621b-page 37 ? 2015 microchip technology inc. 6.6 configuration registers the configuration registers control general globa l functionality that affe cts the entire device. 6.6.1 configuration - 20h bit 7 - timeout - enables the timeout and id le functionality of the smbus protocol. ? ?0? (default for functional revision c) - the smbus tim eout and idle functionality are disabled. the smbus inter- face will not time out if the clock line is held low. likewise, it will not reset if both the data and clock lines are held high for longer than 200us. this is used for i 2 c compliance. ? ?1? (default for functional revision b) - the smbus ti meout and idle functionality are enabled. the smbus inter- face will time out if the clock line is held low for longer than 30ms. likewise, it will reset if both the data and clock lines are held high for longer than 200us. bit 6 - wake_cfg - configures the operation of the wake pin. ? ?0? (default) - the wake pin is not asserted when a touch is detected while the device is in standby. it will still be used to wake the device from deep sleep when driven high. ? ?1? - the wake pin will be asse rted high when a touch is detected while th e device is in standby. it will also be used to wake the device from deep sleep when driven high. bit 5 - dis_dig_noise - determines w hether the digital noise threshold (see section 6.19, "sensor input noise thresh- old register" ) is used by the device. setting this bit disables the feature. ? ?0? - the digital noise threshold is used. if a delta coun t value exceeds the noise threshold but does not exceed the touch threshold, the sample is discarded and not used for the automatic re-calibration routine. ? ?1? (default) - the noise threshold is disabled. any delta count that is less than the touch threshold is used for the automatic re-calibration routine. bit 4 - dis_ana_noise - determines whether the analog noise filter is enabled. setting th is bit disables the feature. ? ?0? (default) - if low frequency noise is detected by the analog block, the delta count on the corresponding channel is set to 0. note that th is does not require that noise status bits be set. ? ?1? - a touch is not blocked even if low frequency noise is detected. bit 3 - max_dur_en - determines whether the maximum duration recalibration is enabled. ? ?0? (default) - the maximum duration recalibration functi onality is disabled. a touch may be held indefinitely and no re-calibration will be performed on any sensor input. ? ?1? - the maximum duration recalibration functionality is enabled. if a touch is hel d for longer than the max_dur bit settings, then the re-calibrati on routine will be restarted (see section 6.8 ). 0 1 1 1 128x 1 0 0 0 256x all others 256x (default = 1111b) table 6-10: configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 20h r/w configuration timeout wake_ cfg dis_ dig_ noise dis_ ana_ noise max_ dur_en --- a0h (rev b) 20h (rev c) 44h r/w configuration 2 inv_link_ tran alt_ pol blk_pwr_ ctrl blk_pol_ mir show_ rf_ noise dis_ rf_ noise - int_ rel_n 40h table 6-9: base_shift bit decode (continued) base_shift[3:0] data scaling factor 32 1 0
? 2015 microchip technology inc. ds00001621b-page 38 CAP1166 6.6.2 configuration 2 - 44h bit 7 - inv_link_tran - determines the behavior of the linked led transition controls (see section 6.29 ). ? ?0? (default) - the linked led transition controls set the min duty cycle equal to the max duty cycle. ? ?1? - the linked led transition controls will invert the t ouch signal. for example, a touch signal will be inverted to a non-touched signal. bit 6 - alt_pol - determines the alert# pin polarity and behavior. ? ?0? - the alert# pin is active high and push-pull. ? ?1? (default) - the alert# pin is active low and open drain. bit 5 - blk_pwr_ctrl - determines whether the device will reduce power consumption while waiting between con- version time completion and the end of the polling cycle. ? ?0? (default) - the device will always power down as much as possible during the time between the end of the last conversion and the end of the polling cycle. ? ?1? - the device will not power down the cap sensor duri ng the time between the end of the last conversion and the end of the polling cycle. bit 4 - blk_pol_mir - determines whether the led mirror contro l register bits are linked to the led polarity bits. set- ting this bit blocks the normal behavior wh ich is to automatically se t and clear the led mirror control bits when the led polarity bits are set or cleared. ? ?0? (default) - when the led polarity controls are set, t he corresponding led mirror co ntrol is automatically set. likewise, when the led polarity contro ls are cleared, the corresponding le d mirror control is also cleared. ? ?1? - when the led polarity controls are set, the corre sponding led mirror control is not automatically set. bit 3 - show_rf_noise - determines whether the noise stat us bits will show rf noise as the only input source. ? ?0? (default) - the noise status regi sters will show both rf noise and low frequency emi noise if either is detected on a capacitive touch sensor input. ? ?1? - the noise status registers will only show rf noise if it is detected on a capacitive touch sensor input. emi noise will still be detected and touches will be blocked norma lly; however, the status bits will not be updated. bit 2 - dis_rf_noise - determines whether the rf noise filt er is enabled. setting this bit disables the feature. ? ?0? (default) - if rf noise is detected by the analog block, the delta count on the corresponding channel is set to 0. note that this does not require that noise status bits be set. ? ?1? - a touch is not blocked even if rf noise is detected. bit 0 - int_rel_n - controls the interrupt behav ior when a release is detected on a button. ? ?0? (default) - an interrupt is generated when a press is detected and again when a release is detected and at the repeat rate (if enabled - see section 6.13 ). ? ?1? - an interrupt is generated when a press is detected and at the repeat rate but not when a release is detected. 6.7 sensor input enable registers the sensor input enable regist ers determine whether a capaci tive touch sensor input is included in the sampling cycle. the length of the sampling cycle is not affe cted by the number of sensor inputs measured. bit 5 - cs6_en - enables the cs6 input to be included during the sampling cycle. ? ?0? - the cs6 input is not included in the sampling cycle. ? ?1? (default) - the cs6 input is included in the sampling cycle. bit 4 - cs5_en - enables the cs5 input to be included during the sampling cycle. bit 3 - cs4_en - enables the cs4 input to be included during the sampling cycle. bit 2 - cs3_en - enables the cs3 input to be included during the sampling cycle. table 6-11: sensor input enable registers addrr/wregister b7 b6 b5b4b3b2b1b0default 21h r/w sensor input enable - - cs6_en cs5_en cs4_en cs3_en cs2_en cs1_en 3fh
CAP1166 ds00001621b-page 39 ? 2015 microchip technology inc. bit 1 - cs2_en - enables the cs2 input to be included during the sampling cycle. bit 0 - cs1_en - enables the cs1 input to be included during the sampling cycle. 6.8 sensor input configuration register the sensor input configuration regist er controls timings associated with the capacitive sensor inputs 1 - 6. bits 7 - 4 - max_dur[3:0] - (default 1010b) - determines the ma ximum time that a sensor p ad is allowed to be touched until the capacitive touch sensor in put is recalibrated, as shown in ta b l e 6 - 1 3 . bits 3 - 0 - rpt_rate[3:0] - (default 0100b) determines the time duration between interrupt assertions when auto repeat is enabled. the resolution is 35ms the range is from 35ms to 560ms as shown in ta b l e 6 - 1 4 . table 6-12: sensor input configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 22h r/w sensor input configuration max_dur[3:0] rpt_rate[3:0] a4h table 6-13: max_dur bit decode max_dur[3:0] time before recalibration 32 1 0 0 0 0 0 560ms 0 0 0 1 840ms 0 0 1 0 1120ms 0 0 1 1 1400ms 0 1 0 0 1680ms 0 1 0 1 2240ms 0 1 1 0 2800ms 1 1 1 3360ms 1 0 0 0 3920ms 1 0 0 1 4480ms 1 0 1 0 5600ms (default) 1 0 1 1 6720ms 1 1 0 0 7840ms 1 1 0 1 8906ms 1 1 1 0 10080ms 1 1 1 1 11200ms table 6-14: rpt_rate bit decode rpt_rate[3:0] interrupt repeat rate 3210 0000 35ms 0001 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms (default) 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms
? 2015 microchip technology inc. ds00001621b-page 40 CAP1166 6.9 sensor input configuration 2 register bits 3 - 0 - m_press[3:0] - (default 0111b) - determines th e minimum amount of time that sensor inputs configured to use auto repeat must detect a sensor pa d touch to detect a ?press and hold? even t. if the sensor input detects a touch for longer than the m_press[3:0] settings, a ?press and hold? event is detected. if a sensor input detects a touch for less than or equal to the m_press[3:0] settings, a to uch event is detected. the resolution is 35ms the range is from 35ms to 560ms as shown in ta b l e 6 - 1 6 . 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms table 6-15: sensor input configuration 2 register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 23h r/w sensor input configuration 2 - - - - m_press[3:0] 07h table 6-16: m_press bit decode m_press[3:0] m_press settings 3210 0000 35ms 0001 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms (default) 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms table 6-14: rpt_rate bit decode (continued) rpt_rate[3:0] interrupt repeat rate 3210
CAP1166 ds00001621b-page 41 ? 2015 microchip technology inc. 6.10 averaging and sampling configuration register the averaging and sampling configuration register controls the number of samples taken and the total sensor input cycle time for all active sensor inputs while the device is functioning in active state. bits 6 - 4 - avg[2:0] - determines the number of samples that are taken for all active channels during the sensor cycle as shown in ta b l e 6 - 1 8 . all samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of sa mples measured before updating the measured results. for example, if cs1, cs2, and cs3 are sa mpled during the sensor cycle, and the avg[ 2:0] bits are set to take 4 samples per channel, then the full sensor cycle will be: cs1, cs1, cs1, cs1, cs2, cs2, cs2, cs2, cs3, cs3, cs3, cs3. bits 3 - 2 - samp_time[1:0] - determines the time to take a single sample as shown in ta b l e 6 - 1 9 . bits 1 - 0 - cycle_time[1:0] - determines the overall cycl e time for all measured channels during normal operation as shown in table 6-20 . all measured channels are sampled at the beginning of the cycle time. if additional time is remain- ing, then the device is placed into a lower power state for the remaining duration of the cycle. table 6-17: averaging and sampling configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 24h r/w averaging and sampling config avg[2:0] samp_time[1:0] cycle_time [1:0] 39h table 6-18: avg bit decode avg[2:0] number of samples taken per measurement 210 000 1 001 2 010 4 0 1 1 8 (default) 100 16 101 32 110 64 1 1 1 128 table 6-19: samp_time bit decode samp_time[1:0] sample time 10 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms table 6-20: cycle_time bit decode cycle_time[1:0] overall cycle time 10 00 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms
? 2015 microchip technology inc. ds00001621b-page 42 CAP1166 application note: the programmed cycle time is only maintained if the total averaging ti me for all samples is less than the programmed cycle. the avg[2:0] bits will take pr iority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate t he number of samples to be measured. 6.11 calibration activate register the calibration activate register forces the respective sens or inputs to be re-calibrated affecting both the analog and digital blocks. during the re-cal ibration routine, the sensor inputs will no t detect a press for up to 600ms and the sensor input base count register values will be invalid. during this time, any press on the corresponding sensor pads will inval- idate the re-calibration. when finished, the calx[9:0] bits will be updated (see section 6.39 ). when the corresponding bit is set, the device will perform the calibration and the bit will be automatically cleared once the re-calibration routine has finished. bit 5 - cs6_cal - when set, the cs6 input is re-calibrated. this bit is automatically cleared once the sensor input has been re-calibrated successfully. bit 4 - cs5_cal - when set, the cs5 input is re-calibrated. this bit is automatically cleared once the sensor input has been re-calibrated successfully. bit 3 - cs4_cal - when set, the cs4 input is re-calibrated. this bit is automatically cleared once the sensor input has been re-calibrated successfully. bit 2 - cs3_cal - when set, the cs3 input is re-calibrated. this bit is automatically cleared once the sensor input has been re-calibrated successfully. bit 1 - cs2_cal - when set, the cs2 input is re-calibrated. this bit is automatically cleared once the sensor input has been re-calibrated successfully. bit 0 - cs1_cal - when set, the cs1 input is re-calibrated. this bit is automatically cleared once the sensor input has been re-calibrated successfully. 6.12 interrupt enable register the interrupt enable register determines whether a sensor pad touch or release (if enabled) causes the interrupt pin to be asserted. bit 5 - cs6_int_en - enables the interrupt pin to be assert ed if a touch is detected on cs6 (associated with the cs6 status bit). ? ?0? - the interrupt pin will not be asserted if a touch is detected on cs6 (associated with the cs6 status bit). ? ?1? (default) - the interrupt pin will be asserted if a touch is detected on cs6 (associated with the cs6 status bit). bit 4 - cs5_int_en - enables the interrupt pin to be assert ed if a touch is detected on cs5 (associated with the cs5 status bit). bit 3 - cs4_int_en - enables the interrupt pin to be assert ed if a touch is detected on cs4 (associated with the cs4 status bit). bit 2 - cs3_int_en - enables the interrupt pin to be assert ed if a touch is detected on cs3 (associated with the cs3 status bit). bit 1 - cs2_int_en - enables the interrupt pin to be assert ed if a touch is detected on cs2 (associated with the cs2 status bit). table 6-21: calibration activate register addrr/wregisterb7 b6 b5b4b3b2b1b0default 26h r/w calibration activate -- cs6_ cal cs5_ cal cs4_ cal cs3_ cal cs2_ cal cs1_ cal 00h table 6-22: interrupt enable register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 27h r/w interrupt enable -- cs6_ int_en cs5_ int_en cs4_ int_en cs3_ int_en cs2_ int_en cs1_ int_en 3fh
CAP1166 ds00001621b-page 43 ? 2015 microchip technology inc. bit 0 - cs1_int_en - enables the interrupt pin to be assert ed if a touch is detected on cs1 (associated with the cs1 status bit). 6.13 repeat rate enable register the repeat rate enable register enables the rep eat rate of the sensor inputs as described in section 5.6.1 . bit 5 - cs6_rpt_en - enables the repeat rate for capacitive touch sensor input 6. ? ?0? - the repeat rate for cs6 is disabled. it will only generate an interrupt when a touch is detected and when a release is detected no matter how long the touch is held for. ? ?1? (default) - the repeat rate for cs6 is enabled. in the ca se of a ?touch? event, it will generate an interrupt when a touch is detected and a release is detected (as determined by the int_rel_n bit - see section 6.6 ). in the case of a ?press and hold? event, it will generate an interrupt when a touch is detected and at the repeat rate so long as the touch is held. bit 4 - cs5_rpt_en - enables the repeat rate for capacitive touch sensor input 5. bit 3 - cs4_rpt_en - enables the repeat rate for capacitive touch sensor input 4. bit 2 - cs3_rpt_en - enables the repeat rate for capacitive touch sensor input 3. bit 1 - cs2_rpt_en - enables the repeat rate for capacitive touch sensor input 2. bit 0 - cs1_rpt_en - enables the repeat rate for capacitive touch sensor input 1. 6.14 multiple touch configuration register the multiple touch configurati on register controls the settings for the mult iple touch detection circuitry. these settings determine the number of simultaneous buttons that may be pr essed before additional buttons are blocked and the mult status bit is set. bit 7 - mult_blk_en - enables the multiple button blocking circuitry. ? ?0? - the multiple touch circuitry is disabl ed. the device will not block multiple touches. ? ?1? (default) - the multiple touch circuitry is enabled . the device will flag the number of touches equal to pro- grammed multiple touch threshold and block all others. it will remember which sensor inputs are valid and block all others until that sensor pad has been released. once a sensor pad has been released, the n detected touches (determined via the cycle order of cs1 - cs6) will be flagged and all others blocked. bits 3 - 2 - b_mult_t[1:0] - determines the number of simult aneous touches on all sensor pads before a multiple touch event is detected and sensor inputs are blocked. the bit decode is given by table 6-25 . table 6-23: repeat rate enable register addrr/wregisterb7b6b5b4b3b2b1b0default 28h r/w repeat rate enable -- cs6_ rpt_en cs5_ rpt_en cs4_ rpt_en cs3_ rpt_en cs2_ rpt_en cs1_ rpt_en 3fh table 6-24: multiple touch configuration addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 2ah r/w multiple touch config mult_ blk_ en - - - b_mult_t[1:0] - - 80h table 6-25: b_mult_t bit decode b_mult_t[1:0] number of simult aneous touches 10 0 0 1 (default) 01 2 10 3 11 4
? 2015 microchip technology inc. ds00001621b-page 44 CAP1166 6.15 multiple touch pattern configuration register the multiple touch pattern configuration register controls th e settings for the multiple t ouch pattern detection circuitry. this circuitry works like the multiple touch det ection circuitry with the following differences: 1. the detection threshold is a percentage of the touch detection threshold as defined by the mtp_th[1:0] bits whereas the multiple touch circuitry uses the touch detection threshold. 2. the mtp detection circuitry either will detect a specific pattern of sensor inputs as determined by the multiple touch pattern register settings or it will use the multiple touch pattern register settings to determine a minimum number of sensor inputs that will cause the mtp circuitr y to flag an event. when using pattern recognition mode, if all of the sensor inputs set by the multiple touc h pattern register have a delt a count greater than the mtp threshold or have their corresponding noise flag status bi ts set, the mtp bit will be set. when using the absolute number mode, if the number of sensor inputs with thresholds above the mtp threshold or with noise flag status bits set is equal to or greater than this number, the mtp bit will be set. 3. when an mtp event occurs, all touches are blocked and an interrupt is generated. 4. all sensor inputs will remain blocked so long as the requ isite number of sensor inpu ts are above the mtp thresh- old or have noise flag status bits set. once this condition is removed, touc h detection will be restored. note that the mtp status bit is only cleared by writing a ?0 ? to the int bit once the condition has been removed. bit 7 - mtp_en - enables the multiple touch pattern detection circuitry. ? ?0? (default) - the mtp detection circuitry is disabled. ? ?1? - the mtp detection circuitry is enabled. bits 3-2 - mtp_th[1:0] - determine the mtp threshold, as shown in ta b l e 6 - 2 7 . this threshold is a percentage of sensor input threshold (see section 6.18, "sensor i nput threshold registers" ) when the device is in the fully active state or of the standby threshold (see section 6.23, "standby threshold register" ) when the device is in the standby state. bit 1 - comp_ptrn - determines whether the mtp detection circ uitry will use the multiple t ouch pattern register as a specific pattern of sensor inputs or as an absolute number of sensor inputs. ? ?0? (default) - the mtp detection circui try will use the multiple touch pattern r egister bit settings as an absolute minimum number of sensor inputs that must be above the th reshold or have noise flag status bits set. the num- ber will be equal to the number of bits set in the register. ? ?1? - the mtp detection circuitry will use pattern recognitio n. each bit set in the multiple touch pattern register indicates a specific sensor input that must have a delta count greater than the mtp threshold or have a noise flag status bit set. if the criteria are met, the mtp status bit will be set. bit 0 - mtp_alert - enables an interrupt if an mtp event oc curs. in either condition, the mtp status bit will be set. ? ?0? (default) - if an mtp event occurs, the alert# pin is not asserted. ? ?1? - if an mtp event occurs, the alert# pin will be asserted. table 6-26: multiple touch pattern configuration addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 2bh r/w multiple touch pattern config mtp_ en - - mtp_th[1:0] comp_ ptrn mtp_ alert 00h table 6-27: mtp_th bit decode mtp_th[1:0] threshold divide setting 10 0 0 12.5% (default) 0125% 1037.5% 1 1 100%
CAP1166 ds00001621b-page 45 ? 2015 microchip technology inc. 6.16 multiple touch pattern register the multiple touch pattern register acts as a pattern to i dentify an expected sensor inpu t profile for diagnostics or other significant events. there are two methods for how the multiple touch pattern register is used: as specific sensor inputs or number of sensor input t hat must exceed the mtp threshold or have no ise flag status bits set. which method is used is based on the comp_ptrn bit (see section 6.15 ). the methods are described below. 1. specific sensor inputs: if, during a single polling cycl e, the specific sensor inpu ts above the mtp threshold or with noise flag status bits set match those bits set in the multiple touch pattern register, an mtp event is flagged. 2. number of sensor inputs: if, during a single polling cycl e, the number of sensor inputs with a delta count above the mtp threshold or with noise flag status bits set is equ al to or greater than the num ber of pattern bits set, an mtp event is flagged. bit 5 - cs6_ptrn - determines whether cs6 is cons idered as part of the multiple touch pattern. ? ?0? - cs6 is not considered a part of the pattern. ? ?1? - cs6 is considered a part of the pattern or the absolu te number of sensor inputs that must have a delta count greater than the mtp threshold or have the no ise flag status bit set is increased by 1. bit 4 - cs5_ptrn - determines whether cs5 is cons idered as part of the multiple touch pattern. bit 3 - cs4_ptrn - determines whether cs4 is cons idered as part of the multiple touch pattern. bit 2 - cs3_ptrn - determines whether cs3 is cons idered as part of the multiple touch pattern. bit 1 - cs2_ptrn - determines whether cs2 is cons idered as part of the multiple touch pattern. bit 0 - cs1_ptrn - determines whether cs1 is cons idered as part of the multiple touch pattern. 6.17 recalibration configuration register the recalibration configuration register controls the automatic re-calibration routine se ttings as well as advanced con- trols to program the sensor input threshold register settings. bit 7 - but_ld_th - enables setting all sensor input thresh old registers by writing to the sensor input 1 threshold register. ? ?0? - each sensor input x threshold register is updated individually. ? ?1? (default) - writing the sensor input 1 threshold regist er will automatically overwrit e the sensor input threshold registers for all sensor inputs (sensor input threshold 1 through sensor input threshold 6). the individual sensor input x threshold registers (sensor input 2 threshold th rough sensor input 6 threshold) can be individually updated at any time. bit 6 - no_clr_intd - controls whether the accumulation of in termediate data is cleared if the noise status bit is set. ? ?0? (default) - the accumulation of intermediate data is cleared if the noise status bit is set. ? ?1? - the accumulation of intermediate data is not cleared if the noise status bit is set. application note: bits 5 and 6 should both be set to the same value. either both should be set to ?0? or both should be set to ?1?. bit 5 - no_clr_neg - controls whether the consecutive negativ e delta counts counter is cleared if the noise status bit is set. table 6-28: multiple to uch pattern register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 2dh r/w multiple touch pattern -- cs6_ ptrn cs5_ ptrn cs4_ ptrn cs3_ ptrn cs2_ ptrn cs1_ ptrn 3fh table 6-29: recalibration configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 2fh r/w recalibration configuration but_ ld_th no_ clr_ intd no_ clr_ neg neg_delta_ cnt[1:0] cal_cfg[2:0] 8ah
? 2015 microchip technology inc. ds00001621b-page 46 CAP1166 ? ?0? (default) - the consecutive negative delta counts counter is cleared if the noise status bit is set. ? ?1? - the consecutive negative delta counts counter is not cleared if the noise status bit is set. bits 4 - 3 - neg_delta_cnt[1:0] - determines the number of negative delta counts necessary to trigger a digital re- calibration as shown in table 6-30 . bits 2 - 0 - cal_cfg[2:0] - determines the update time and nu mber of samples of the automatic re-calibration routine. the settings apply to all sensor inputs universally (though individual sensor inputs can be configured to support re-cal- ibration - see section 6.11 ). note 6-1 recalibration samples refers to the number of sa mples that are measured and averaged before the base count is updated however does no t control the base count update period. note 6-2 update time refers to the amount of time (in polling cycle periods) that elapses before the base count is updated. the time will depend upon the nu mber of channels active, the averaging setting, and the programmed cycle time. table 6-30: neg_delta_cnt bit decode neg_delta_cnt[1:0] number of consecutive negative delta count values 10 00 8 0 1 16 (default) 10 32 1 1 none (disabled) table 6-31: cal_cfg bit decode cal_cfg[2:0] recalibration samples (see note 6-1 ) update time (see note 6-2 ) 210 0 0 0 16 16 001 32 32 0 1 0 64 64 (default) 0 1 1 128 128 100 256 256 1 0 1 256 1024 1 1 0 256 2048 1 1 1 256 4096
CAP1166 ds00001621b-page 47 ? 2015 microchip technology inc. 6.18 sensor input threshold registers the sensor input threshold registers store the delta thresh old that is used to determi ne if a touch has been detected. when a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. if the sensor input change exceeds the threshold settings, a touch is detected. when the but_ld_th bit is set (see section 6.17 - bit 7), writing data to the sensor input 1 threshold register will update all of the sensor input thresh old registers (31h - 35h inclusive). 6.19 sensor input noise threshold register the sensor input noise threshold regist er controls the value of a secondary internal threshold to detect noise and improve the automatic recalibration routine. if a capacitive touch sensor input exceeds the sensor input noise threshold but does not exceed the sensor input thre shold, it is determined to be caused by a noise spike. that sample is not used by the automatic re-calibration routine. this featur e can be disabled by setting the dis_dig_noise bit. bits 1-0 - cs1_bn_th[1:0] - controls the noise threshold for all capacitive touch sensor inputs, as shown in ta b l e 6 - 3 4 . the threshold is proportional to the threshold setting. 6.20 standby channel register table 6-32: sensor input threshold registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 30h r/w sensor input 1 threshold -6432168421 40h 31h r/w sensor input 2 threshold -6432168421 40h 32h r/w sensor input 3 threshold -6432168421 40h 33h r/w sensor input 4 threshold -6432168421 40h 34h r/w sensor input 5 threshold -6432168421 40h 35h r/w sensor input 6 threshold -6432168421 40h table 6-33: sensor input noise threshold register addrr/w register b7 b6 b5b4b3b2b1b0default 38h r/w sensor input noise threshold cs_bn_th [1:0] 01h table 6-34: csx_bn_th bit decode cs_bn_th[1:0] percent threshold setting 10 0025% 0 1 37.5% (default) 1050% 1 1 62.5% table 6-35: standby channel register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 40h r/w standby channel - - cs6_ stby cs5_ stby cs4_ stby cs3_ stby cs2_ stby cs1_ stby 00h
? 2015 microchip technology inc. ds00001621b-page 48 CAP1166 the standby channel register controls which (if any) capacitive touch sensor inputs are active during standby. bit 5 - cs6_stby - controls whether the cs6 channel is active in standby. ? ?0? (default) - the cs6 channel not be sampled during standby mode. ? ?1? - the cs6 channel will be sampled during standby mode. it will use the standby threshold setting, and the standby averaging and sensitivity settings. bit 4 - cs5_stby - controls whether the cs5 channel is active in standby. bit 3 - cs4_stby - controls whether the cs4 channel is active in standby. bit 2 - cs3_stby - controls whether the cs3 channel is active in standby. bit 1 - cs2_stby - controls whether the cs2 channel is active in standby. bit 0 - cs1_stby - controls whether the cs1 channel is active in standby. 6.21 standby configuration register the standby configuration regist er controls averaging and cycle time for thos e sensor inputs that are active in standby. this register is useful for detecting proximity on a small nu mber of sensor inputs as it a llows the user to change aver- aging and sample times on a limited number of sensor inputs and still maintain normal functionality in the fully active state. bit 7 - avg_sum - determines whether the active sensor inputs will average the programmed number of samples or whether they will accumulate for the programmed number of samples. ? ?0? - (default) - the active sensor input delta count values will be based on the average of the programmed number of samples when compared against the threshold. ? ?1? - the active sensor input delta count values will be based on the summation of the programmed number of samples when compared against the threshold. this bit sh ould only be set when performing proximity detection as a physical touch will overflow the delta count registers and may result in false readings. bits 6 - 4 - stby_avg[2:0] - determines the number of samples that are taken for all active channels during the sensor cycle as shown in ta b l e 6 - 3 7 . all samples are taken consecutively on the same channel before the next channel is sam- pled and the result is averaged over the number of sa mples measured before updating the measured results. bit 3-2 - stby samp_time[1:0] - determines the time to take a single sample when the device is in standby as shown in table 6-38 . table 6-36: standby configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 41h r/w standby config- uration avg_ sum stby_avg[2:0] stby_samp_ time[1:0] stby_cy_time [1:0] 39h table 6-37: stby_avg bit decode stby_avg[2:0] number of samples taken per measurement 210 000 1 001 2 010 4 0 1 1 8 (default) 100 16 101 32 110 64 1 1 1 128
CAP1166 ds00001621b-page 49 ? 2015 microchip technology inc. bits 1 - 0 - stby_cy_time[2:0] - determines the overall cycle time for all measured channels during standby operation as shown in table 6-39 . all measured channels are sa mpled at the beginning of the cycle time. if additional time is remaining, the device is placed into a lower powe r state for the remaini ng duration of the cycle. application note: the programmed cycle time is only maintained if the total averaging ti me for all samples is less than the programmed cycle. the stby_avg[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. 6.22 standby sensitivity register the standby sensitivity register cont rols the sensitivity for sensor in puts that are active in standby. bits 2 - 0 - stby_sense[2:0] - controls the sensitivity for se nsor inputs that are active in standby. the sensitivity set- tings act to scale the relative delta coun t value higher or lo wer based on the system paramete rs. a setting of 000b is the most sensitive while a setting of 111b is the least sensitive. at the more sensitive settings, touches are detected for a smaller delta c corresponding to a ?lighter? touch. these se ttings are more sensitive to noise however and a noisy envi- ronment may flag more false touches than higher sensitivity levels. application note: a value of 128x is the most sens itive setting available. at the most sensitivity settings, the msb of the delta count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a c of 25ff from a 10pf base capacitance). conversely a val ue of 1x is the least sensitiv e setting available. at these settings, the msb of the delta count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a c of 3.33pf from a 10pf base capacitance). table 6-38: stby_samp_time bit decode stby_samp_time[1:0] sampling time 10 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms table 6-39: stby_cy_time bit decode stby_cy_time[1:0] overall cycle time 10 00 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms table 6-40: standby sensitivity register addrr/w register b7 b6 b5b4b3b2b1b0default 42h r/w standby sensitiv- ity - - - - - stby_sense[2:0] 02h table 6-41: stby_sense bit decode stby_sense[2:0] sensitivity multiplier 210 0 0 0 128x (most sensitive) 001 64x
? 2015 microchip technology inc. ds00001621b-page 50 CAP1166 6.23 standby threshold register the standby threshold register stores t he delta threshold that is used to dete rmine if a touch ha s been detected. when a touch occurs, the input signal of the corresponding sens or pad changes due to the capacitance associated with a touch. if the sensor input change exceeds the threshold settings, a touch is detected. 6.24 sensor input base count registers the sensor input base count registers store the calibrated ?not touched? input value from the capacitive touch sensor inputs. these registers are periodically u pdated by the re-calibration routine. the routine uses an internal adder to add the current coun t value for each reading to the sum of the previous readings until sample size has been reached. at this point, the uppe r 16 bits are taken and used as the sensor input base count. the internal adder is then reset and the re-calibration routine continues. the data presented is determined by the base_shift[3:0] bits (see section 6.5 ). 6.25 led output type register 0 1 0 32x (default) 011 16x 100 8x 101 4x 110 2x 1 1 1 1x - (least sensitive) table 6-42: standby threshold register addrr/w register b7 b6 b5b4b3b2b1b0default 43h r/w standby thresh- old -6432168421 40h table 6-43: sensor input base count registers addrr/w register b7 b6 b5b4b3b2b1b0default 50h r sensor input 1 base count 128 64 32 16 8 4 2 1 c8h 51h r sensor input 2 base count 128 64 32 16 8 4 2 1 c8h 52h r sensor input 3 base count 128 64 32 16 8 4 2 1 c8h 53h r sensor input 4 base count 128 64 32 16 8 4 2 1 c8h 54h r sensor input 5 base count 128 64 32 16 8 4 2 1 c8h 55h r sensor input 6 base count 128 64 32 16 8 4 2 1 c8h table 6-44: led output type register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 71h r/w led output type -- led6_ ot led5_ ot led4_ ot led3_ ot led2_ ot led1_ ot 00h table 6-41: stby_sense bit decode (continued) stby_sense[2:0] sensitivity multiplier 210
CAP1166 ds00001621b-page 51 ? 2015 microchip technology inc. the led output type register controls th e type of output for the led pins. each pin is controlled by a single bit. refer to application note 21.4 CAP1166family led configuratio n options for more information about implementing leds. bit 5 - led6_ot - determines the output type of the led6 pin. ? ?0? (default) - the led6 pin is an open-drain output wi th an external pull-up resistor. when the appropriate pin is set to the ?active? state (logic ?1?), the pin will be driven low. conversely, when the pin is set to the ?inactive? state (logic ?0?), then the pin will be left in a high z state and pulled high via an external pull-up resistor. ? ?1? - the led6 pin is a push-pull output. when driving a l ogic ?1?, the pin is driven high. when driving a logic ?0?, the pin is driven low. bit 4 - led5_ot - determines the output type of the led5 pin. bit 3 - led4_ot - determines the output type of the led4 pin. bit 2 - led3_ot - determines the output type of the led3 pin. bit 1 - led2_ot - determines the output type of the led2 pin. bit 0 - led1_ot - determines the output type of the led1 pin. 6.26 sensor input led linking register the sensor input led linking register controls whether a ca pacitive touch sensor input is linked to an led output. if the corresponding bit is set, then the appropriate led ou tput will change states defined by the led behavior controls (see section 6.31 ) in response to the capacitive touch sensor input. bit 5 - cs6_led6 - links the led6 output to a detected to uch on the cs6 sensor input. w hen a touch is detected, the led is actuated and will behave as dete rmined by the led behavior controls. ? ?0? (default) - the led6 output is not associated with the cs6 input. if a touch is detected on the cs6 input, the led will not automatically be actuated. the led is enable d and controlled via the led output control register (see section 6.28 ) and the led behavior registers (see section 6.31 ). ? ?1? - the led6 output is associated with the cs6 inpu t. if a touch is detected on the cs6 input, the led will be actuated and behave as defined in ta b l e 6 - 5 2 . bit 4 - cs5_led5 - links the led5 output to a detected to uch on the cs5 sensor input. w hen a touch is detected, the led is actuated and will behave as dete rmined by the led behavior controls. bit 3 - cs4_led4 - links the led4 output to a detected to uch on the cs4 sensor input. w hen a touch is detected, the led is actuated and will behave as dete rmined by the led behavior controls. bit 2 - cs3_led3 - links the led3 output to a detected to uch on the cs3 sensor input. w hen a touch is detected, the led is actuated and will behave as dete rmined by the led behavior controls. bit 1 - cs2_led2 - links the led2 output to a detected to uch on the cs2 sensor input. w hen a touch is detected, the led is actuated and will behave as dete rmined by the led behavior controls. bit 0 - cs1_led1 - links the led1 output to a detected to uch on the cs1 sensor input. w hen a touch is detected, the led is actuated and will behave as dete rmined by the led behavior controls. 6.27 led polarity register table 6-45: sensor input led linking register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 72h r/w sensor input led linking --cs6_ led6 cs5_ led5 cs4_ led4 cs3_ led3 cs2_ led2 cs1_ led1 00h table 6-46: led polarity register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 73h r/w led polarity - - led6_ pol led5_ pol led4_ pol led3_ pol led2_ pol led1_ pol 00h
? 2015 microchip technology inc. ds00001621b-page 52 CAP1166 the led polarity register controls the lo gical polarity of the led outputs. when t hese bits are set or cleared, the corre- sponding led mirror controls are also set or cl eared (unless the blk_pol_mir bit is set - see section 6.6, "configu- ration registers" ). table 6-48, "led polarity behavior" shows the interaction betwe en the polarity controls, output controls, and relative brightness. application note: the polarity controls determine the final led pin drive. a touch on a linked capacitive touch sensor input is treated in the same way as the le d output control bit being set to a logic ?1?. application note: the led drive assumes that the leds are confi gured such that if the led pin is driven to a logic ?0? then the led will be on and that th e CAP1166 led pin is sinking the led current. conversely, if the led pin is driven to a logic ?1?, the led will be off and there is no current flow. see figure 5-1, "system diagram for CAP1166". application note: this application note applies when the led polari ty is inverted (ledx_pol = ?0?). for led operation, the duty cycle se ttings determine the % of time th at the led pin will be driven to a logic ?0? state in. the max duty cycle settings define the maximum % of time that the led pin will be driven low (i.e. maximu m % of time that the led is on ) while the min duty cycle settings determine the minimum % of time that the led pin will be driven low (i.e. minimum % of time that the led is on ). when there is no touch detected or the led output control register bit is at a logic ?0 ?, the led output will be driven at the minimum duty cycle setting. breathe operations will ramp the duty cycle fr om the minimum duty cycle to the maximum duty cycle. application note: this application note applies when the led polarity is non-inverted (ledx_pol = ?1?). for led operation, the duty cycle settings determine th e % of time that the led pin will be driven to a logic ?1? state. the max duty cycle setti ngs define the maximum % of time that the led pin will be driven high (i.e. maximum % of time that the led is off ) while the min duty cycle settings determine the minimum % of time t hat the led pin will be driven high (i.e. minimum % of time that the led is off ). when there is no touch detect ed or the led output control register bit is at a logic ?0?, the led outp ut will be driven at 100 minus the minimum duty cycle setting. breathe operations will ramp the duty cycle from 100 minus the minimum duty cycle to 100 minus the maximum duty cycle. application note: the led mirror controls (see section 6.30, "led mirror control register" ) work with the polarity controls with respect to led brightness but will not have a direct effect on the output pin drive. bit 5 - led6_pol - determines the polarity of the led6 output. ? ?0? (default) - the led6 output is inverted. for example, a setting of ?1? in the led output control register will cause the led pin output to be driven to a logic ?0?. ? ?1? - the led6 output is non-inverted. for example, a setting of ?1? in the led output control register will cause the led pin output to be driven to a logic ?1? or left in the high-z state as determined by its output type. bit 4 - led5_pol - determines the polarity of the led5 output. bit 3 - led4_pol - determines the polarity of the led4 output. bit 2 - led3_pol - determines the polarity of the led3 output. bit 1 - led2_pol - determines the polarity of the led2 output. bit 0 - led1_pol - determines the polarity of the led1 output. 6.28 led output control register the led output control register contro ls the output state of the led pins th at are not linked to sensor inputs. table 6-47: led output control register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 74h r/w led output control -- led6_ dr led5_ dr led4_ dr led3_ dr led2_ dr led1_ dr 00h
CAP1166 ds00001621b-page 53 ? 2015 microchip technology inc. the led polarity control register will determine the non actuated state of the led pins . the actuated led behavior is determined by the led behavior controls (see section 6.31, "led behavior registers" ). table 6-48 shows the interaction between the polarity cont rols, output controls, a nd relative brightness. bit 5 - led6_dr - determines whether led6 output is driven high or low. ? ?0? (default) - the led6 output is driven at the minimum duty cycle or not actuated. ? ?1? - the led6 out put is driven at the maximum duty cycle or is actuated. bit 4 - led5_dr - determines whether led5 output is driven high or low. bit 3 - led4_dr - determines whether led4 output is driven high or low. bit 2 - led3_dr - determines whether led3 output is driven high or low. bit 1 - led2_dr - determines whether led2 output is driven high or low. bit 0 - led1_dr - determines whether led1 output is driven high or low. 6.29 linked led transition control register the linked led transition control register controls the led drive wh en the led is linked to a capacitive touch sensor input. these controls work in conj unction with the inv_ link_tran bit (see section 6.6.2, "configuration 2 - 44h" ) to create smooth transitions from host control to linked leds. note: if an led is linked to a sensor input in the sensor input led linking register ( section 6.26, "sensor input led linking register" ), the corresponding bit in the led output control register is ignored (i.e. a linked led cannot be host controlled). table 6-48: led polarity behavior led output control register or touch polarity max duty min duty brightness led appearance 0 inverted (?0?) not used minimum % of time that the led is on (logic 0) maximum brightness at min duty cycle on at min duty cycle 1 inverted (?0?) maximum % of time that the led is on (logic 0) minimum % of time that the led is on (logic 0) maximum brightness at max duty cycle. bright- ness ramps from min duty cycle to max duty cycle according to led behavior 0 non-inverted (?1?) not used minimum % of time that the led is off (logic 1) maximum brightness at 100 minus min duty cycle. on at 100 - min duty cycle 1 non-inverted (?1?) maximum % of time that the led is off (logic 1) minimum % of time that the led is off (logic 1) for direct behavior, maximum brightness is 100 minus max duty cycle. when breath- ing, max brightness is 100 minus min duty cycle. brightness ramps from 100 - min duty cycle to 100 - max duty cycle. according to led behavior table 6-49: linked led transition control register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 77h r/w linked led tran- sition control -- led6_ ltran led5_ ltran led4_ ltran led3_ ltran led2_ ltran led1_ ltran 00h
? 2015 microchip technology inc. ds00001621b-page 54 CAP1166 bit 5 - led6_ltran - determines the transitio n effect when led6 is linked to cs6. ? ?0? (default) - when the led output control bit for led6 is ?1?, and then led6 is linked to cs6 and no touch is detected, the led will change states. ? ?1? - if the inv_link_tran bit is ?1?, when the led output control bit for cs6 is ?1?, and then cs6 is linked to led6 and no touch is detected, the led will not change states. in addition, the led state will change when the sensor pad is touched. if the inv_link_tran bi t is ?0?, when the led output control bit for cs6 is ?1?, and then cs6 is linked to led6 and no touch is detected, the led will no t change states. however, the led state will not change when the sensor pad is touched. application note: if the led behavior is not ?direct? and the inv _link_tran bit it ?0?, the led will not perform as expected when the led6_ltran bit is set to ?1?. therefore, if breathe and pulse behaviors are used, set the inv_link_tran bit to ?1?. bit 4 - led5_ltran - determines the transitio n effect when led5 is linked to cs5. bit 3 - led4_ltran - determines the transitio n effect when led4 is linked to cs4. bit 2 - led3_ltran - determines the transitio n effect when led3 is linked to cs3. bit 1 - led2_ltran - determines the transitio n effect when led2 is linked to cs2. bit 0 - led1_ltran - determines the transitio n effect when led1 is linked to cs1. 6.30 led mirror control register the led mirror control re gisters determine the meaning of duty cycle settings when pol arity is non-inverted for each led channel. when the polarity bit is set to ?1? (non-inv erted), to obtain correct steps for led ramping, pulse, and breathe behaviors, the min and max duty cycles need to be rela tive to 100%, rather than the default, which is relative to 0%. application note: the led drive assumes that the leds are confi gured such that if the led pin is driven to a logic ?0?, the led will be on and the CAP1166 led pin is sinking the led current. when the polarity bit is set to ?1?, it is considered n on-inverted. for systems using the opposite led configuration, mirror controls would apply when the polarity bit is ?0?. these bits are changed automatically if the corresponding led polarity bit is changed (unless the blk_pol_mir bit is set - see section 6.6 ). bit 5 - led6_mir_en - determines whether the duty cycle settings are ?biased? relative to 0% or 100% duty cycle. ? ?0? (default) - the duty cycle settings are determined relati ve to 0% and are determined directly with the settings. ? ?1? - the duty cycle settings are determined relative to 100%. bit 4 - led5_mir_en - determines whether the duty cycle settings are ?biased? relative to 0% or 100% duty cycle. bit 3 - led4_mir_en - determines whether the duty cycle settings are ?biased? relative to 0% or 100% duty cycle. bit 2 - led3_mir_en - determines whether the duty cycle settings are ?biased? relative to 0% or 100% duty cycle. bit 1 - led2_mir_en - determines whether the duty cycle settings are ?biased? relative to 0% or 100% duty cycle. bit 0 - led1_mir_en - determines whether the duty cycle settings are ?biased? relative to 0% or 100% duty cycle. table 6-50: led mirror control register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 79h r/w led mirror con- trol -- led6_ mir _ en led5_ mir _ en led4_m ir_ en led3_ mir_ en led2_ mir _ en led1_ mir _ en 00h
CAP1166 ds00001621b-page 55 ? 2015 microchip technology inc. 6.31 led behavior registers the led behavior registers control the operation of leds. each led pin is controlled by a 2-bit field and the behavior is determined by whether the led is linked to a capacitive touch sensor input or not. if the corresponding led output is linked to a capacitive touch sensor input, the appropriate behavior will be enabled / disabled based on touches and releases. if the led output is not associated with a capacitive touc h sensor input, the appropriate behavior will be enabled / dis- abled by the led output control register. if the respective ledx_dr bit is set to a logic ?1?, this will be associated as a ?touch?, and if the ledx_dr bit is set to a logic ?0?, this will be associated as a ?release?. table 6-52, "ledx_ctl bit decode" shows the behavior triggers. the defined behavior will activate when the start trig- ger is met and will stop when the stop trigger is met. note the behavior of the breathe hold and pulse release option. the led polarity control register will determin e the non actuated state of the led outputs (see section 6.27, "led polarity register" ). application note: if an led is not linked to a capacitive touch sensor input and is br eathing (via the breathe or pulse behaviors), it must be unactuated and then re-actua ted before changes to behavior are processed. for example, if the led ou tput is breathing and th e maximum duty cycle is changed, this change will not take effect until the led output cont rol register is set to ?0? and then re-set to ?1?. application note: if an led is not linked to the capacitive touc h sensor input and conf igured to operate using pulse 1 behavior, then the circuitry will onl y be actuated when the corresponding output control bit is set. it will not check the bit condi tion until the pulse 1 behavior is finished. the device will not remember if the bit was cleared and reset while it was actuated. application note: if an led is actuated and not linked and t he desired led behavior is changed, this new behavior will take effect immediately; howeve r, the first instance of the changed behavior may act incorrectly (e.g. if changed from direct to pulse 1, the led output may ?breathe? 4 times and then end at minimum duty cycle). led behaviors will operate normally once the led has been un-actuated and then re-actuated. application note: if an led is actuated and it is switched from linked to a ca pacitive touch sensor input to unlinked (or vice versa), the led will respond to the new command source immediately if the behavior was direct or breathe. for puls e behaviors, it will complete the behavior already in progress. for example, if a linked led was actuated by a touch and the control is changed so that it is un linked, it will check the status of the corresponding led output control bit. if that bit is ?0?, then the led will behave as if a releas e was detected. likewise, if an unlinked led was actuated by the led output control regist er and the control is changed so that it is linked and no touch is detected, then the led will behave as if a release was detected. 6.31.1 led behavior 1 - 81h bits 7 - 6 - led4_ctl[1:0] - determines the behavior of led4 as shown in ta b l e 6 - 5 2 . bits 5 - 4 - led3_ctl[1:0] - determines the behavior of led3 as shown in ta b l e 6 - 5 2 . bits 3 - 2 - led2_ctl[1:0] - determines the behavior of led2 as shown in ta b l e 6 - 5 2 . bits 1 - 0 - led1_ctl[1:0] - determines the behavior of led1 as shown in ta b l e 6 - 5 2 . 6.31.2 led behavior 2 - 82h bits 3 - 2 - led6_ctl[1:0] - determines the behavior of led6 as shown in ta b l e 6 - 5 2 . bits 1 - 0 - led5_ctl[1:0] - determines the behavior of led5 as shown in ta b l e 6 - 5 2 . table 6-51: led behavior registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 81h r/w led behavior 1 led4_ctl[1:0] led3_ctl[1:0] led2_ctl[1:0] led1_ctl[1:0] 00h 82h r/w led behavior 2 - - - - led6_ctl[1:0] led5_ctl[1:0] 00h
? 2015 microchip technology inc. ds00001621b-page 56 CAP1166 application note: the pwm frequency is determined based on the selected led behavior, the programmed breathe period, and the programmed min and max duty cycles. for the direct behavior mode, the pwm frequency is calculated based on the programmed rise and fall times. if these are set at 0, then the maximum pwm frequency will be used based on the programmed duty cycle settings. 6.32 led pulse 1 period register the led pulse period 1 register determines the overall per iod of a pulse operation as determined by the led_ctl registers (see ta b l e 6 - 5 2 - setting 01b). the lsb represents 32ms so t hat a setting of 18h (24d) would represent a period of 768ms (24 x 32ms = 768ms). the total range is from 32ms to 4.064 seconds as shown in ta b l e 6 - 5 4 with the default being 1024ms. application note: due to constraints on the led drive pwm operation, any breathe period less than 160ms (05h) may not be achievable. the device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. bit 7 - st_trig - determines the start trigger for the led pulse behavior. ? ?0? (default) - the led will pulse when a t ouch is detected or the drive bit is set. ? ?1? - the led will pulse when a release is detected or the drive bit is cleared. table 6-52: ledx_ctl bit decode ledx_ctl [1:0] operation description start trigger stop trigger 10 0 0 direct the led is driven to the programmed state (active or inactive). see figure 6-7 touch detected or led output con- trol bit set release detected or led output control bit cleared 01 pulse 1 the led will ?pulse? a programmed number of times. during each ?pulse? the led will breathe up to the maximum brightness and back down to the minimum brightness so that the total ?pulse? period matches the pro- grammed value. touch or release detected or led output control bit set or cleared (see section 6.32 ) n/a 1 0 pulse 2 the led will ?pulse? when the start trigger is detected. when the stop trigger is detected, it will ?pulse? a programmable number of times then return to its minimum brightness. touch detected or led output con- trol bit set release detected or led output control bit cleared 1 1 breathe the led will breathe. it will be driven with a duty cycle that ramps up from the pro- grammed minimum duty cycle (default 0%) to the programmed maximum duty cycle duty cycle (default 100%) and then back down. each ramp takes up 50% of the programmed period. the total period of each ?breath? is determined by the led breathe period con- trols - see section 6.34 . touch detected or led output con- trol bit set release detected or led output control bit cleared table 6-53: led pulse 1 period register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 84h r/w led pulse 1 period st_ trig p1_ per6 p1_ per5 p1_ per4 p1_ per3 p1_ per2 p1_ per1 p1_ per0 20h
CAP1166 ds00001621b-page 57 ? 2015 microchip technology inc. the pulse 1 operation is shown in figure 6-1 when the led output is configured for non-inverted polarity (ledx_pol = 1) and in figure 6-2 for inverted polarity (ledx_pol = 0). . figure 6-1: pulse 1 behavior with non-inverted polarity figure 6-2: pulse 1 behavior with inverted polarity table 6-54: led pulse / breathe period example setting (hex) setting (decimal) to tal breathe / pulse period (ms) 00h 0 32 01h 1 32 02h 2 64 03h 3 96 . . . . . . . . . 7dh 125 4000 normal ? untouched operation normal ? untouched operation touch detected or release detected (100% - pulse 1 max duty cycle) * brightness x pulses after touch or after release pulse 1 period (p1_per) (100% - pulse 1 min duty cycle) * brightness led brightness normal ? untouched operation normal ? untouched operation touch detected or release detected pulse 1 min duty cycle * brightness x pulses after touch or after release pulse period (p1_per) pulse 1 max duty cycle * brightness led brightness
? 2015 microchip technology inc. ds00001621b-page 58 CAP1166 6.33 led pulse 2 period register the led pulse 2 period register determines the overall per iod of a pulse operation as determined by the led_ctl registers (see ta b l e 6 - 5 2 - setting 10b). the lsb represents 32ms so t hat a setting of 18h (24d) would represent a period of 768ms. the total range is from 32ms to 4.064 seconds (see table 6-54 ) with a default of 640ms. application note: due to constraints on the led drive pwm operation, any breathe period less than 160ms (05h) may not be achievable. the device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. the pulse 2 behavior is shown in figure 6-3 for non-inverted polarity (ledx_pol = 1) and in figure 6-4 for inverted polarity (ledx_pol = 0). 7eh 126 4032 7fh 127 4064 table 6-55: led pulse 2 period register addrr/w register b7 b6b5b4b3b2 b1 b0default 85h r/w led pulse 2 period - p2_ per6 p2_ per5 p2_ per4 p2_ per3 p2_ per2 p2_ per1 p2_ per0 14h figure 6-3: pulse 2 behavior with non-inverted polarity table 6-54: led pulse / breathe period example (continued) setting (hex) setting (decimal) to tal breathe / pulse period (ms) . . . normal ? untouched operation normal ? untouched operation touch detected (100% - pulse 2 min duty cycle) * brightness (100% - pulse 2 max duty cycle) * brightness x additional pulses after release release detected pulse period (p2_per) led brightness
CAP1166 ds00001621b-page 59 ? 2015 microchip technology inc. 6.34 led breathe period register the led breathe period register determines the overall pe riod of a breathe operation as determined by the led_ctl registers (see ta b l e 6 - 5 2 - setting 11b). the lsb represents 32ms so that a setting of 18h (24d) would represent a period of 768ms. the total range is from 32ms to 4.064 seconds (see table 6-54 ) with a default of 2976ms. application note: due to constraints on the led drive pwm operation, any breathe period less than 160ms (05h) may not be achievable. the device wi ll breathe at the minimum period possible as determined by the period and min / max duty cycle settings. 6.35 led configuration register the led configuration register controls general led behavior as well as the num ber of pulses that are sent for the pulse led output behavior. bit 6 - ramp_alert - determines whet her the device will assert the alert# pin when leds ac tuated by the led output control register bits have finished their respective behaviors. interrupts will only be generated if the led activity is generated by writing the led output control registers. any led activity asso ciated with touch detection will not cause an interrupt to be generated when the led behavior has been finished. ? ?0? (default) - the alert# pin will not be asserted when le ds actuated by the led output control register have finished their programmed behaviors. ? ?1? - the alert# pin will be asserted whenever any led that is actuated by the led output control register has finished its programmed behavior. bits 5 - 3 - pulse2_cnt[2:0] - determines the number of pulses used for the pulse 2 behavior as shown in table 6-58 . bits 2 - 0 - pulse1_cnt[2:0] - determines the number of pulses used for the pulse 1 behavior as shown in table 6-58 . figure 6-4: pulse 2 behavior with inverted polarity table 6-56: led brea the period register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 86h r/w led breathe period - br_ per6 br_ per5 br_ per4 br_ per3 br_ per2 br_ per1 br_ per0 5dh table 6-57: led conf iguration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 88h r/w led config - ramp_ alert pulse2_cnt[2:0] p ulse1_cnt[2:0] 04h normal ? untouched operation normal ? untouched operation touch detected pulse 2 max duty cycle * brightness pulse 2 min duty cycle * brightness x additional pulses after release release detected pulse period (p2_per) led brightness . . .
? 2015 microchip technology inc. ds00001621b-page 60 CAP1166 6.36 led duty cycle registers the led duty cycle register s determine the minimum and maximum duty cycle settings us ed for the led for each led behavior. these settings affect the brightness of the led when it is fully off and fully on. the led driver duty cycle will ramp up from the minimum duty cycle to the maximum duty cycle and back down again. application note: when operating in direct behavior mode, changes to the duty cycle settings will be applied immediately. when operating in breathe, puls e 1, or pulse 2 modes, the led must be unactuated and then re-actuated before changes to behavior are processed. bits 7 - 4 - x_max_duty[3:0] - dete rmines the maximum pwm duty cycle for the led drivers as shown in table 6-60 . bits 3 - 0 - x_min_duty[3:0] - de termines the minimum pwm duty cycle fo r the led drivers as shown in ta b l e 6 - 6 0 . table 6-58: pulsex_cnt decode pulsex_cnt[2:0] number of breaths 21 0 0 0 0 1 (default - pulse 2) 00 1 2 01 0 3 01 1 4 1 0 0 5 (default - pulse 1) 10 1 6 11 0 7 11 1 8 table 6-59: led duty cycle registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 90h r/w led pulse 1 duty cycle p1_max_duty[3:0] p1_min_duty[3:0] f0h 91h r/w led pulse 2 duty cycle p2_max_duty[3:0] p2_min_duty[3:0] f0h 92h r/w led breathe duty cycle br_max_duty[3:0] br_min_duty[3:0] f0h 93h r/w direct duty cycle dr_ma x_duty[3:0] dr_mi n_duty[3:0] f0h table 6-60: led duty cycle decode x_max/min_duty [3:0] maximum duty cycle minimum duty cycle 3210 0 0 0 0 7% 0% 0 0 0 1 9% 7% 0010 11% 9% 0 0 1 1 14% 11% 0100 17% 14% 0101 20% 17% 0110 23% 20% 0111 26% 23% 1000 30% 26% 1001 35% 30% 1010 40% 35%
CAP1166 ds00001621b-page 61 ? 2015 microchip technology inc. 6.37 led direct ramp rates register the led direct ramp rates register control the rising and fa lling edge time of an led that is configured to operate in direct behavior mode. the rising edge time corresponds to th e amount of time the led takes to transition from its min- imum duty cycle to its maximum duty cycle. conversely, th e falling edge time corresponds to the amount of time that the led takes to transition from its maxi mum duty cycle to its minimum duty cycle. bits 5 - 3 - rise_rate[2:0] - determines the rising edge time of an led when it transitions from its minimum drive state to its maximum drive state as shown in ta b l e 6 - 6 2 . bits 2 - 0 - fall_rate[2:0] - determines the falling edge time of an led when it transitions from its maximum drive state to its minimum drive state as shown in ta b l e 6 - 6 2 . 6.38 led off delay register the led off delay register determines t he amount of time that an led remains at its maximum duty cycle (or minimum as determined by the polarity controls) befo re it starts to ramp down. if the led is operating in breathe mode, this delay is applied at the top of each ?breath?. if the led is oper ating in the direct mode, this delay is applied when the led is unactuated. 1011 46% 40% 1100 53% 46% 1101 63% 53% 1110 77% 63% 1 1 1 1 100% 77% table 6-61: led direct ramp rates register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 94h r/w led direct ramp rates - - rise_rate[2:0] fall_rate[2:0] 00h table 6-62: rise / fall rate decode rise_rate/ fall_rate/ bit decode rise / fall time (t rise / t fall ) 21 0 00 0 0 0 0 1 250ms 0 1 0 500ms 0 1 1 750ms 10 0 1s 10 1 1.25s 11 0 1.5s 11 1 2s table 6-63: led off delay register addrr/w register b7 b6 b5b4b3b2b1b0default 95h r/w led off delay register - br_off_dly[2:0] dir_off_dly[3:0] 00h table 6-60: led duty cycle decode (continued) x_max/min_duty [3:0] maximum duty cycle minimum duty cycle 3210
? 2015 microchip technology inc. ds00001621b-page 62 CAP1166 bits 6 - 4 - br_off_dly[2:0] - determines the breathe behav ior mode off delay, which is the amount of time an led in breathe behavior mode remains inactive after it finishes a breathe pulse (ramp on and ramp off), as shown in figure 6- 5 (non-inverted polarity ledx_pol = 1) and figure 6-6 (inverted polarity ledx_pol = 0) . available settings are shown in table 6-64 . figure 6-5: breathe behavior with non-inverted polarity figure 6-6: breathe behavior with inverted polarity led actuated 100% - breathe max min cycle * brightness 100% - breathe min duty cycle * brightness led unactuated breathe off delay (br_off_dly) led brightness breathe period (br_per) led actuated breathe max duty cycle * brightness breathe min duty cycle * brightness led unactuated breathe off delay (br_off_dly) led brightness breathe period (br_per)
CAP1166 ds00001621b-page 63 ? 2015 microchip technology inc. bits 3 - 0 - dir_off_dly[3:0] - determines the turn-off delay, as shown in ta b l e 6 - 6 5 , for all leds that are configured to operate in direct behavior mode. the direct behavior operation is determined by the combi nation of programmed rise time, fall time, min and max duty cycles, off delay, and polarity. figure 6-7 shows the behavior for non-inverted polarity (ledx_pol = 1) while figure 6- 8 shows the behavior for inverted polarity (ledx_pol = 0). table 6-64: breathe off delay settings br_off_dly [2:0] off delay 210 0 0 0 0 (default) 0 0 1 0.25s 010 0.5s 0 1 1 0.75s 100 1.0s 1 0 1 1.25s 110 1.5s 111 2.0s figure 6-7: direct behavior for non-inverted polarity figure 6-8: direct behavior for inverted polarity normal ? untouched operation rise_rate setting (t rise ) (100% - max duty cycle) * brightness touch detected release detected off delay (t off_dly ) fall_rate setting (t fall ) normal ? untouched operation (100% - min duty cycle) * brightness led brightness normal ? untouched operation rise_rate setting (t rise ) min duty cycle * brightness touch detected release detected off delay (t off_dly ) fall_rate setting (t fall ) normal ? untouched operation max duty cycle * brightness led brightness
? 2015 microchip technology inc. ds00001621b-page 64 CAP1166 6.39 sensor input calibration registers the sensor input calibration registers hold the 10-bi t value that represents the last calibration value. table 6-65: off delay decode off delay[3:0] bit decode off delay (t off_dly ) 32 1 0 00 0 0 0 0 0 0 1 250ms 0 0 1 0 500ms 0 0 1 1 750ms 01 0 0 1s 01 0 1 1.25s 0 1 1 0 1.5s 01 1 1 2s 1 0 0 0 2.5s 1 0 0 1 3.0s 1 0 1 0 3.5s 1 0 1 1 4.0s 1 1 0 0 4.5s all others 5.0s table 6-66: sensor inpu t calibration registers addr register r/w b7 b6 b5 b4 b3 b2 b1 b0 default b1h sensor input 1 calibration r cal1_9 cal1_8 cal1_7 cal1_6 cal1_5 cal1_4 cal1_3 cal1_2 00h b2h sensor input 2 calibration r cal2_9 cal2_8 cal2_7 cal2_6 cal2_5 cal2_4 cal2_3 cal2_2 00h b3h sensor input 3 calibration r cal3_9 cal3_8 cal3_7 cal3_6 cal3_5 cal3_4 cal3_3 cal3_2 00h b4h sensor input 4 calibration r cal4_9 cal4_8 cal4_7 cal4_6 cal4_5 cal4_4 cal4_3 cal4_2 00h b5h sensor input 5 calibration r cal5_9 cal5_8 cal5_7 cal5_6 cal5_5 cal5_4 cal5_3 cal5_2 00h b6h sensor input 6 calibration r cal6_9 cal6_8 cal6_7 cal6_6 cal6_5 cal6_4 cal6_3 cal6_2 00h b9h sensor input calibration lsb 1 r cal4_1 cal4_0 cal3_1 cal3_0 cal2_1 cal2_0 cal1_1 cal1_0 00h bah sensor input calibration lsb 2 r - - - - cal6_1 cal6_0 cal5_1 cal5_0 00h
CAP1166 ds00001621b-page 65 ? 2015 microchip technology inc. 6.40 product id register the product id register stores a unique 8-bit value that identifies the device. 6.41 manufacturer id register the vendor id register stores an 8-bit value that represents microchip. 6.42 revision register the revision register stores an 8-bit va lue that represents the part revision. table 6-67: product id register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default fdhr product id 01010001 51h table 6-68: vendor id register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default feh rmanufacturer id01011101 5dh table 6-69: revision register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default ffhr revision 10000011 83h
? 2015 microchip technology inc. ds00001621b-page 66 CAP1166 7.0 package information 7.1 CAP1166 package drawings note: for the most current package drawings, se e the microchip packaging specification at: http://www.microchip.com/packaging. figure 7-1: 24-pin ssop package drawing
CAP1166 ds00001621b-page 67 ? 2015 microchip technology inc. figure 7-2: 24-pin ssop package dimensions
? 2015 microchip technology inc. ds00001621b-page 68 CAP1166 figure 7-3: CAP1166 pcb land pattern - 24-pin ssop
CAP1166 ds00001621b-page 69 ? 2015 microchip technology inc. figure 7-4: 20-pin qfn 4mm x 4 mm package drawing
? 2015 microchip technology inc. ds00001621b-page 70 CAP1166 figure 7-5: 20-pin qfn 4mm x 4mm package dimensions figure 7-6: 20-pin qfn 4mm x 4mm pcb drawing
CAP1166 ds00001621b-page 71 ? 2015 microchip technology inc. 7.2 package marking figure 7-7: CAP1166 package markings - 20-pin qfn figure 7-8: CAP1166 package markings - 24-pin ssop c 166 - 1 ywwnnna rcc e3 top bottom bottom marking not allowed pb-free/green symbol (matte sn) lines 1-3: line 4: center horizontal alignment left horizontal alignment pin 1 0.41 3x 0.56 line 1 ? smsc logo without circled r symbol line 2 ? device id, version line 3 ? year, week, alphanumeric traceability code line 4 ? revision, country code 1 e3 top bottom pb-free/green symbol (matte sn) pin 1 0.6 2x 1.5pt line 1 ? smsc logo with circled r symbol line 2 ? device id, version line 3 ? revision, year, week, traceability code line 2 ? vendor code, country code pin 1 c a11 6 6 p 1 - y wnnna w ? r b b9 3 v vcc - v line 1 ? engineering code 2x 1.5pt
? 2015 microchip technology inc. ds00001621b-page 72 CAP1166 appendix a: device delta a.1 delta from cap1066 to CAP1166 1. updated circuitry to improve power supply rejection. 2. updated led driver duty cycl e decode values to have more distribution at lower values - closer to a logarithmic curve. see table 6-60, "led duty cycle decode" . 3. updated bug that breathe periods were not correct above 2.6s. this includes rise / fall time decodes above 1.5s. 4. added filtering on reset pi n to prevent errant resets. 5. updated controls so that the reset pin assertion places the device into the lowest power state available and causes an interrupt when released. see section 5.2, "reset pin" . 6. added 1 bit to the led off delay register (see section 6.38, "led off delay register" ) to extend times from 2s to 5s in 0.5s intervals. 7. breathe behavior modified. a breathe off delay control was added to the led off delay register (see section 6.38, "led off delay register" ) so the leds can be configured to remain inactive between breathes. 8. added controls for the led transition effects when linking leds to capacitive sensor inputs. see section 6.29, "linked led transition control register" . 9. added controls to ?mirror? the led duty cycle outputs so that when polarity changes, the led brightness levels look right. these bits are automatically set when polarity is set. added control to break this auto-set behavior. see section 6.30, "led mirror control register" . 10. added multiple touch patter n detection circuitry. see section 6.15, "multiple touch pattern configuration regis- ter" . 11. added general status register to flag multiple touches , multiple touch pattern issues and general touch detec- tions. see section 6.2, "status registers" . 12. added bits 6 and 5 to the recalibration configuration register (2fh - see section 6.17, "recalibration configura- tion register" ). these bits control whether the accumulation of intermediate data and the consecutive negative delta counts counter are cleared when the noise status bit is set. 13. added configuration 2 register for led linking controls, noise detection contro ls, and control to interrupt on press but not on release. added control to change alert pin polarity. see section 6.6, "configuration registers" . 14. updated deep sleep behavior so that device does no t clear dsleep bit on received communications but will wake to communicate. 15. changed pwm frequency for led drivers. the pwm fr equency was derived from the programmed breathe period and duty cycle settings and it ranged from ~4hz to ~8000 hz. the pwm frequency has been updated to be a fixed value of ~2000hz. 16. register delta: table a.1 register delta from cap1066 to CAP1166 address register delta delta default 00h page 33 changed - main status / control added bits 7-6 to control gain 00h 02h page 34 new - general status new register to store mtp, mult, led, reset, and general touch bits 00h 44h page 37 new - configuration 2 new register to control alert polarity, led touch linking behavior, led output behav- ior, and noise detection, and interrupt on release 40h 24h page 41 changed - averaging control updated register bits - moved samp_avg[2:0] bits and added samp_- time bit 1. default changed 39h 2bh page 44 new - multiple touch pattern configuration new register for multiple touch pattern configuration - enable and threshold set- tings 80h
CAP1166 ds00001621b-page 73 ? 2015 microchip technology inc. 2dh page 45 new - multiple touch pattern register new register for multiple touch pattern detection circuitry - pattern or number of sensor inputs 3fh 2fh page 45 changed - recalibration configuration updated register - updated cal_cfg bit decode to add a 128 averages setting and removed highest time setting. default changed. added bit 6 no_clr_intd and bit 5 no_clr_neg. 8ah 38h page 47 changed - sensor input noise threshold updated register bits - removed bits 7 - 3 and consolidated all controls into bits 1 - 0. these bits will set the noise threshold for all channels. default changed 01h 39h removed - noise threshold register 2 removed register n/a 41h page 48 changed - standby con- figuration updated register bits - moved stby_avg[2:0] bits and added stby_- time bit 1. default changed 39h 77h page 53 new - linked led tran- sition control new register to control transition effect when led linked to sensor inputs 00h 79h page 54 new - led mirror control new register to control led output mirror- ing for brightness control when polarity changed 00h 90h page 60 changed - led pulse 1 duty cycle changed bit decode to be more logarithmic f0h 91h page 60 changed - led pulse 2 duty cycle changed bit decode to be more logarithmic f0h 92h page 60 changed - led breathe duty cycle changed bit decode to be more logarithmic f0h 93h page 60 changed - led direct duty cycle changed bit decode to be more logarithmic f0h 95h added controls - led off delay added bits 6-4 br_off_dly[2:0] added bit 3 dir_off_dly[3] 00h fdh page 65 changed - product id changed bit decode for CAP1166 51h table a.1 register delta from cap1066 to CAP1166 (continued) address register delta delta default
? 2015 microchip technology inc. ds00001621b-page 74 CAP1166 appendix b: data sheet revision history revision section/figure/entry correction ds00001621b (02-09-15) features, ta b l e 2 - 1 , table 2- 2, "pin types" , section 5.0, "general description" references to bc-link in terface, bc_data, bc_- clk, bc-irq#, bc-link bus have been removed application note under table 2-6 [bc-link] hidden in data sheet table 3-2, "electrical specifi- cations" bc-link timing section hidden in data sheet table 4-1 protocol used for 68k pull down resistor changed from ?bc-link communications? to ?reserved? section 4.2.2, "smbus address and rd / wr bit" replaced ?client address? with ?slave address? in this section. section 4.2.4, smbus ack and nack bits , section 4.2.5, smbus stop bit , section 4.2.7, smbus and i2c compatibility replaced ?client? with ?slave? in these sections. table 4-4, "read byte proto- col" heading changed from ?client address? to ?slave address? table 6-1 register name for register address 77h changed from ?led linked transition control? to ?linked led transition control? section 6.30 changed cs6 to led6 table 6-53 modified b3 bit name section 7.7 package marking updated package drawing appendix a: device delta changed 2dh to 2fh in item #12 product identificat ion system removed bc-link references rev a rev a replaces previous smsc version rev. 1.32 (01-05-12) rev. 1.32 (01-05-12) table 3-2, "electrical specifi- cations" added conditions for t hd:dat . section 4.2.7, "smbus and i2c compatibility" renamed from ?smbus and i2c compliance.? first paragraph, added last sentence: ?for informa- tion on using the cap1188 in an i 2 c system, refer to smsc an 14.0 smsc dedi cated slave devices in i 2 c systems.? added: cap1188 supports i 2 c fast mode at 400khz. this covers the smbus max time of 100khz. section 6.4, "sensor input delta count registers" changed negative value cap from ffh to 80h. rev. 1.31 (08-18-11) section 4.3.3, "smbus send byte" added an application note: t he send byte protocol is not functional in deep sleep (i.e., dsleep bit is set). section 4.3.4, "smbus receive byte" added an application note: the receive byte proto- col is not functional in d eep sleep (i.e., dsleep bit is set). rev. 1.3 (05-18-11) section 6.42, "revision reg- ister" updated revision id from 82h to 83h. rev. 1.2 (02-10-11) section a.8, "delta from rev b (mask b0) to rev c (mask b1)" added.
CAP1166 ds00001621b-page 75 ? 2015 microchip technology inc. table 2-1, "pin description for CAP1166" changed value in ?unused connection? column for the addr_comm pin from ?connect to ground? to ?n/a?. table 3-2, "electrical specifi- cations" psr improvements made in functional revision b. changed psr spec from 100 typ and 200 max counts / v to 3 and 10 counts / v. conditions updated. section 5.5.2, "recalibrating sensor inputs" added more detail with subheadings for each type of recalibration. section 6.6, "configuration registers" added bit 5 blk_pwr_ctrl to the configuration 2 register 44h. the timeout bit is set to ?1? by default for functional revision b and is set to ?0? by default for functional revision c. section 6.42, "revision reg- ister" updated revision id in register ffh from 81h to 82h. rev. 1.1 (11-17-10) document updated for f unctional revision b. see section a.7, "delta from rev a (mask a0) to rev b (mask b0)". cover added to general description: ?includes circuitry and support for enhanced sensor proximity detection.? added the following features: calibrates for parasitic capacitance analog filtering for system noise sources press and hold feature for volume-like applications table 3-2, "electrical specifi- cations" conditions for power supply rejection modified add- ing the following: sampling time = 2.56ms averaging = 1 negative delta counts = disabled all other parameters default section 6.11, "calibration acti- vate register" updated register description to indicate which re-cal- ibration routine is used. section 6.14, "multiple touch configuration register" updated register descripti on to indicate what will happen. table 6-34, "csx_bn_th bit decode" table heading changed from ?threshold divide set- ting? to ?percent threshold setting?. section 7.0, "package infor- mation" added pcb land pattern. CAP1166-1 added in an ssop package. rev. 1.0 (06-14-10) initial release revision section/figure/entry correction
? 2015 microchip technology inc. ds00001621b-page 76 CAP1166 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification servic e helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://www.microchip.com/support
? 2015 microchip technology inc. ds00001621b-page 77 CAP1166 product identification system to order or obtain information, e.g., on pricing or deliv ery, refer to the factory or the listed sales office. part no. [x] - 1 - xxx - [x] (1) l l l l device temperature package tape and reel range option examples: note 1: tape and reel identifier only appears in the catalog part number description. this i dentifier is used for ordering purposes and is not printed on the devic e package. check with your microchip sales office for package availability with the tape and reel option. device: CAP1166 temperature range: blank = 0 c to +85 c (extended commercial) package: bp = qfn czc = ssop tape and reel option: tr = tape and reel (1) CAP1166-1-bp-tr 20-pin qfn 4mm x 4mm (rohs compliant) six capacitive touch sensor inputs, six led drivers, dedicated wake, reset, smbus / bc-link / spi interfaces reel size is 4,000 pieces CAP1166-1-czc-tr 24-pin ssop (rohs compliant) six capacitive touch sensor inputs, six led drivers, dedicated wake, reset, smbus / bc-link / spi interfaces reel size is 2,500 pieces
? 2015 microchip technology inc. ds00001621b-page 78 CAP1166 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with y our specifications. microchip make s no representations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising fr om this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, i ndemnify and hold harmless microchip from any and all dama ges, claims, suits, or expenses resulting from such use. no licenses ar e conveyed, implic- itly or otherwise, under any micr ochip intellectual property rights. trademarks the microchip name and logo, t he microchip logo, dspic, flas hflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of mi crochip technology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tr ademarks of microchip technol ogy incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kl eernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem .net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, view span, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are pr operty of their respective companies. ? 2015, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn: 9781632770318 microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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